LPC810M021FN8 datasheet(67/71 Pages) NXP

67 / 71 page

LPC81xM

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Product data sheet

Rev. 3 — 29 July 2013

67 of 71

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

19. Revision history

Table 27.

Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC81XM v.3

20130729

Product data sheet

LPC81XM v.2.1

• Operating temperature range changed to -40 °C to 105 °C.

• Type numbers updated to reflect the new operating temperature range. See Table 1

“Ordering information” and Table 2 “Ordering options”.

• ISP entry pin moved from PIO0_1 to PIO0_12 for TSSOP, and SSOP packages. See

Table 4 and Table 6.

• Propagation delay values updated in Table 21 “Comparator characteristics”.

• SPI characteristics updated. See Section 12.6.

• IRC characteristics updated. See Section 12.3.

• CoreMark data updated. See Figure 19 and Figure 20.

• IRC frequency changed to 12 MHz +/- 1.5 %. See Table 13.

• Data sheet status updated to Product data sheet.

LPC81XM v.2.1

20130325

Preliminary data sheet -

LPC81XM v.2

• Editorial updates (temperature sensor removed).

• CoreMark data added. See Figure 19 “Active mode: CoreMark power consumption

IDD” and Figure 20 “CoreMark score”.

• IDD in Deep power-down mode added for condition Low-power oscillator on/WKT

wake-up enabled. See Table 10.

• Table note 3 updated for Table 4 “Pin description table (fixed pins)”.

• Conditions for ter and tprog updated in Table 12 “Flash characteristics”.

• Section 13.3 “Internal voltage reference” added.

• Typical timing data added for SPI. See Section 12.6.

• Typical timing data added for USART in synchronous mode. See Section 12.7.

• BOD characterization added. See Section 13.1.

• IRC characterization added. See Section 12.3.

• Internal voltage reference characteristics added. See Section 13.3.

• Data sheet status changed to Preliminary data sheet.

LPC81XM v.2

20130128

Objective data sheet

LPC81XM v.1

Modifications:

• MTB memory space changed to 1 kB in Figure 6.

• Electrical pin characteristics added in Table 10.

• Figure 11 “Connecting the SWD pins to a standard SWD connector” added.

• Peripheral power consumption added in Table 11.

• Table 7 updated.

• MRT implementation changed to 31-bit timer.

• Power consumption data in active and sleep mode with IRC added. See Figure 13 to

Figure 15.

• Power consumption (parameter IDD) in active and sleep mode for low-power mode at

12 MHz corrected in Table 10.

• Power consumption (parameter IDD) in active and sleep mode at 24 MHz added in

Table 10.

• Maximum USART speed in synchronous mode changed to 10 Mbit/s.

• Section 5 “Marking” added.

LPC81XM v.1

20121112

Objective data sheet

LPC810M021FN8 Datasheet(PDF) 67 Page - NXP Semiconductors

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