AD9854AST datasheet(14/52 Pages) AD

14 / 52 page

AD9854

Rev. E | Page 14 of 52

Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 200 MHz reference clock with the

REFCLK multiplier bypassed vs. a 20 MHz reference clock and the REFCLK multiplier enabled at 10×.

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

5kHz/

SPAN 50kHz

Figure 16. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

200 MHz REFCLK with REFCLK Multiplier Bypassed

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

5kHz/

SPAN 50kHz

Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

20 MHz REFCLK with REFCLK Multiplier = 10×

–100

–110

–150

–120

–130

–140

–160

–170

AOUT = 80MHz

AOUT =5MHz

FREQUENCY (Hz)

100

100k

10k

Figure 18. Residual Phase Noise,

300 MHz REFCLK with REFCLK Multiplier Bypassed

FREQUENCY (Hz)

–90

–100

–140

–110

–120

–130

–150

–160

100

100k

10k

AOUT =80MHz

AOUT =5MHz

Figure 19. Residual Phase Noise,

30 MHz REFCLK with REFCLK Multiplier = 10×

DAC CURRENT (mA)

Figure 20. SFDR vs. DAC Current, 59.1 AOUT,

300 MHz REFCLK with REFCLK Multiplier Bypassed

FREQUENCY (MHz)

620

615

610

605

600

595

590

100

120

140

Figure 21. Supply Current vs. Output Frequency (Variation Is Minimal,

Expressed as a Percentage, and Heavily Dependent on Tuning Word)

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