Circuit Note

CN-0164

Rev. A | Page 3 of 5

START

START ADC

TRANSMIT

VALUE

50µA

NO

NO

NO

1MIN?

START

N

INTERRUPT

FROM

ADF7020?

PACKAGE

RECEIVED?

200µA

25mA

NO

ADC

FINISHED?

READ ADC

LINEARIZE

AIR DATA LINK

READ ADF7020

DATA

SEND DATA

TO PC

PUT DATA IN SERIAL

BUFFER

MEASURING NODE

MAIN LOOP

RECEIVING NODE

MAIN LOOP

Figure 2. Measuring and Receiving Node Main Loop Flowcharts

Code Description—ADF7020 Driver

There are many modulation schemes supported by the

ADF7020. In this case, the GFSK (gaussian frequency shift

keying) is used. This has the benefit of having very good

spectral efficiency. In this mode, the ADF7020 generates the

data clock both when transmitting and receiving. The rising

edge of this clock (DATA CLK) generates an interrupt, which

causes the ADuC7060 to place the data on the output port, bit-

by-bit as shown in Figure 3. When all the data has been

clocked-out, the chip select is deasserted, and the ADuC7060

reenters deep sleep mode.

On the receiving side, the ADF7020 generates an interrupt

when a matching sync word is received (Port INT/LOCK goes

high for nine clock cycles)

This informs the ADuC7060 processor to prepare for the

reception of a package. Each bit that is received from the

package causes an interrupt in the ADuC7060. In the interrupt

service routine (ISR), the bit stream is read and stored in a

buffer. When all the bytes in the package have been received, a

flag is set to indicate that a new package has been received. The

main loop can now ensure the validity of the package by the

checksum. A correct and complete package can be processed. In

this case, this information is sent via the UART to the PC for

display. The same ISR handles both the sending and receiving of

data to/from the ADF7020 transceiver, as shown in Figure 4.

Source code for this circuit can be found at this address:

www.analog.com/CN0164_Source_Code.