Circuit Note

CN-0279

Rev. 0 | Page 3 of 5

Figure 5. Generalized Differential Amplifier/ADC Interface with Band-Pass Filter

Filter and Interface Design Procedure

In this section, a general approach to the design of the amplifier/

ADC interface with a band-pass filter is presented. To achieve

optimum performance (bandwidth, SNR, and SFDR), there are

certain design constraints placed on the general circuit by the

amplifier and the ADC.

1. The amplifier must see the correct dc load recommended

by the data sheet for optimum performance.

2. The correct amount of series resistance must be used between

the amplifier and the load presented by the filter. This is to

prevent undesired peaking in the pass band.

3. The input to the ADC must be reduced by external parallel

resistors, and the correct series resistance must be used to

isolate the ADC from the filter. This series resistor also

reduces peaking.

The generalized circuit shown in Figure 5 applies to most high

speed differential amplifier/ADC interfaces and was used as a

basis for the band-pass filter. This design approach tends to

minimize the insertion loss of the filter by taking advantage of

the relatively high input impedance of most high speed ADCs

and the relatively low impedance of the driving source (amplifier).

The basic design process is as follows:

200 Ω and 400 Ω.

recommendations, typically between 5 Ω and 36 Ω.

3. Calculate the filter load impedance using

less than 10 Ω if the amplifier differential output impedance

output impedance of the amplifier is 12 Ω or less.

is optimum for the particular differential amplifier chosen

using the following equation:

6. Calculate the filter source resistance by

7. Using a filter design program or tables design the filter

of filter, bandwidth, and order. Use a bandwidth that is about

10% higher than the desired bandwidth of the application

pass band to ensure flatness in the frequency span.

After running these preliminary calculations, the circuit must

be given a quick review for the following items.

that the filter is within the limits of most filter tables and

design programs.

to parasitic capacitance and component variations.

several nH.

Sometimes circuit simulators can make these values too

low or too high. To make these values more reasonable,

simply ratio these values with better standard value

components that maintain the same resonant frequency.

In some cases, the filter design program can provide more than

one unique solution, especially with higher order filters. The

solution that uses the most reasonable set of component values

should always be chosen. Also, choose a configuration that ends

in a shunt capacitor so that it can be combined with the ADC

input capacitance.

0.1µF

0.1µF

0.1µF

0.1µF

GAIN

XFMR

1:2 Z

INPUT

Z = 50Ω

INTERNAL

INPUT Z

ADC

INTERNAL

INPUT Z

AVDD_AMP

DRVDD

AVDD

ANALOG

INPUT

0.1µF

VCM