IXTH60N10 datasheet(1/2 Pages) IXYS

Part #	IXTH60N10

Description	N-Channel Enhancement Mode

PDF	2 Pages

Scroll/Zoom	100%

Manufacturer	IXYS [IXYS Corporation]

Direct Link	http://www.ixys.com

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1 / 2 page

Symbol

Test conditions

Maximum ratings

V

DSS

T

J

= 25°C to 150°C

100

V

DGR

T

J

= 25°C to 150°C; R

GS = 1.0 MΩ

100

V

GS

Continuous

±20

V

GSM

Transient

±30

V

I

D25

T

C

= 25

°C MOSFET chip capability

80

A

I

D(RMS)

External lead current limit

75

A

I

DM

T

C

= 25

°C, pulse width limited by T

JM

320

A

I

AR

T

C

= 25

°C80

A

E

AR

T

C

= 25

°C45

mJ

E

AS

T

C

= 25

°C

1.5

J

dv/dt

I

S

≤ I

DM, di/dt ≤ 100 A/µs, VDD ≤ VDSS

5

V/ns

T

J

≤ 150°C, R

G = 2 Ω

P

D

T

C

= 25

°C

300

W

T

J

-55 ... +150

°C

T

JM

150

°C

T

stg

-55 ... +150

°C

T

L

1.6 mm (0.063 in.) from case for 10 s

300

°C

M

d

Mounting torque

1.13/10

Nm/lb.in.

Weight

TO-264

6

g

TO-247 AD (IXTH)

G = Gate

D = Drain

S = Source

TAB = Drain

(TAB)

DS99069(7/03)

Symbol

Test Conditions

Characteristic Values

(T

J = 25°C, unless otherwise specified)

Min. Typ.

Max.

V

DSS

V

GS = 0 V, ID = 250 µA

100

V

GS(th)

V

DS = VGS, ID = 250 µA

2.0

4.0

V

I

GSS

V

GS = ±20 VDC, VDS = 0

±100

nA

I

DSS

V

DS = VDSS

T

J =

25

°C25

µA

V

GS = 0 V

T

J = 125°C

250

µA

R

DS(on)

V

GS = 10 V, ID = 0.5 ID25

20

m

Ω

Pulse test, t

≤ 300 µs, duty cycle d ≤ 2 %

TO-268 (IXTT) Case Style

(TAB)

G

S

HiPerFETTM

Power MOSFETs

IXTH 60N10

V

DSS

= 100

V

IXTT 60N10

I

D25

=

60

A

R

DS(on)

=

20 m

Ω

Advance Technical Information

N-Channel Enhancement Mode

Features

International standard packages

Low R

DS (on) HDMOS

TM

process

Rugged polysilicon gate cell structure

Unclamped Inductive Switching (UIS)

rated

Low package inductance

- easy to drive and to protect

Fast intrinsic Rectifier

Advantages

Easy to mount

Space savings

High power density

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