H5TC2G83DFR datasheet(21/33 Pages) HYNIX

21 / 33 page

Rev. 1.0 / Sep. 2012

Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.

b) DQ signals are MID-LEVEL.

Datab)

1 4-7

repeat Sub-Loop 0, use BA[2:0] = 1 instead

2 8-11

repeat Sub-Loop 0, use BA[2:0] = 2 instead

3 12-15

repeat Sub-Loop 0, use BA[2:0] = 3 instead

4 16-19

repeat Sub-Loop 0, use BA[2:0] = 4 instead

5 20-23

repeat Sub-Loop 0, use BA[2:0] = 5 instead

6 24-17

repeat Sub-Loop 0, use BA[2:0] = 6 instead

7 28-31

repeat Sub-Loop 0, use BA[2:0] = 7 instead

Datab)

1 4-7

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

2 8-11

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2

3 12-15

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3

4 16-19

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4

5 20-23

repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5

6 24-17

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6

7 28-31

repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

H5TC2G83DFR Datasheet(PDF) 21 Page - Hynix Semiconductor