8

Figure 15. Simplified schematic for the MMIC die in the package

Biasing and Operation

The recommended quiescent DC bias condition for

optimum efficiency, performance and reliability is Vd=5

volts with Vg (+0.5V typ.) set to give Id(q)=600 mA. Minor

improvements in performance are possible depending

on the application. The drain bias voltage range is 3 to 5V

and the quiescent drain current biasing range is 400mA to

650mA. A single DC gate supply connected to Vg will bias

all the amplifier stages. Muting can be accomplished by

setting Vg to zero.

A simplified schematic for the MMIC die in the package is

shown in Figure 15. The MMIC die contains ESD and over

voltage protection diodes for Vg, Vd1, and Vd2. ESD diodes

protect all possible ESD or over voltage damages among

Vg to ground, Vg to Vd1, Vg to Vd2, Vd1 to ground and

Vd2 to ground. The typical forward current versus voltage

for 11 diodes connected in series is shown in Figure 16.

The RF input and output are DC blocked internally.

Under the recommended DC quiescent biasing condition

at Vds=5V, Ids=600mA, Vgg=+0.5V, typical gate terminal

current is approximately 0.02mA. If an active biasing

technique is selected for the AMMP6421 MMIC PA DC

biasing, the active biasing circuit must have more than

10-times higher internal current that the gate terminal

current.

The AMMP6421 can be biased either single positive DC

biasing or dual positive supply operation as shown in

Figure 17(a) and (b).

Output

Input