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IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

Configuration Devices for SRAM-Based LUT Devices

January 2012

Altera Corporation

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

The EPC2 device provides JTAG BST circuitry that complies with the IEEE Std.

1149.1-1990 specification. You can perform JTAG BST before or after configuration, but

not during configuration. Table 6 lists the JTAG instructions supported by the EPC2

device.

Devices.

Table 6. EPC2 Device JTAG Instructions

JTAG Instruction

OPCODE

Description

SAMPLE/PRELOAD

00 0101 0101

Allows a snapshot of a signal at the device pins to be captured and

examined during normal device operation and permits an initial data

pattern output at the device pins.

EXTEST

00 0000 0000

Allows the external circuitry and board-level interconnections to be

tested by forcing a test pattern at the output pins and capturing

results at the input pins.

BYPASS

11 1111 1111

Places the 1-bit bypass register between the TDI and TDO pins,

which allows the BST data to pass synchronously through a selected

device to adjacent devices during normal device operation.

IDCODE

00 0101 1001

Selects the device IDCODE register and places it between the TDI

and TDO pins, allowing the device IDCODE to be serially shifted out of

the TDO pin. The device IDCODE for the EPC2 configuration device is

shown below:

0000 0001000000000010 00001101110 1

USERCODE

00 0111 1001

Selects the USERCODE register and places it between the TDI and

TDO

pins, allowing the USERCODE to be serially shifted out of the

TDO

pin. The 32-bit USERCODE is a programmable user-defined

pattern.

INIT_CONF

00 0110 0001

Initiates the FPGA re-configuration process by pulsing the

nINIT_CONF

pin low, which is connected to the FPGAs nCONFIG

pins. After this instruction is updated, the nINIT_CONF pin is pulsed

low when the JTAG state machine enters the Run-Test/Idle state. The

nINIT_CONF

pin is then released and nCONFIG is pulled high by the

resistor after the JTAG state machine goes out of Run-Test/Idle state.

The FPGA configuration starts after the nCONFIG pin goes high. As a

result, the FPGA is configured with the new configuration data stored

in the configuration device. You can add this function to your

programming file (.pof, .jam, .jbc) in the Quartus II software by

enabling the Initiate configuration after programming option in the

Programmer options window (Options menu). This instruction is

also used by the MAX+PLUS II software, .jam files, and .jbc files.

ISP Instructions

—

These instructions are used when programming an EPC2 device

using JTAG ports with a USB-Blaster, MasterBlaster, ByteBlaster II,

EthernetBlaster, or ByteBlasterMV download cable, or using a .jam,

.jbc, or .svf file using an embedded processor.