AD9850SLASHFSPCB datasheet(10/20 Pages) AD

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AD9850

–10–

REV. H

tDS

W0*

tDH

tWH

tWL

tCF

VALID DATA

OLD FREQ (PHASE)

NEW FREQ (PHASE)

*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD

AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK

DATA

W CLK

CLKIN

COS OUT

tDS

DATA SETUP TIME

3.5ns

tDH

DATA HOLD TIME

3.5ns

tWH

W CLK HIGH

3.5ns

tWL

W CLK LOW

3.5ns

tCD

CLK DELAY AFTER FQ_UD

3.5ns

tFH

FQ UD HIGH

7.0ns

tFL

FQ UD LOW

7.0ns

tFD

FQ UD DELAY AFTER W CLK

7.0ns

tCF

OUTPUT LATENCY FROM FQ UD

FREQUENCY CHANGE

18 CLOCK CYCLES

PHASE CHANGE

13 CLOCK CYCLES

SYMBOL

DEFINITION

MINIMUM

tCD

tFD

tFH

tFL

FQ UD

Figure 6. Parallel Load Frequency/Phase Update Timing Sequence

Table III. 8-Bit Parallel Load Data/Control Word Functional Assignment

Word

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2]

Data[1]

Data[0]

Phase-b4

Phase-b3

Phase-b2

Phase-b1

Phase-b0

Power-Down

Control

(MSB)

(LSB)

Freq-b31

Freq-b30

Freq-b29

Freq-b28

Freq-b27

Freq-b26

Freq-b25

Freq-b24

(MSB)

Freq-b23

Freq-b22

Freq-b21

Freq-b20

Freq-b19

Freq-b18

Freq-b17

Freq-b16

Freq-b15

Freq-b14

Freq-b13

Freq-b12

Freq-b11

Freq-b10

Freq-b9

Freq-b8

Freq-b7

Freq-b6

Freq-b5

Freq-b4

Freq-b3

Freq-b2

Freq-b1

Freq-b0

(LSB)

Table II. Factory Reserved Internal Test Control Codes

Loading Format

Factory Reserved Codes

Parallel

1) W0 = XXXXXX10

2) W0 = XXXXXX01

Serial

1) W32 = 1; W33 = 0

2) W32 = 0; W33 = 1

3) W32 = 1; W33 = 1

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