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AD9822JR Datasheet(PDF) 16 Page - Analog Devices

Part # AD9822JR
Description  Complete 14-Bit CCD/CIS Signal Processor
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9822JR Datasheet(HTML) 16 Page - Analog Devices

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AD9822
Rev. B | Page 16 of 20
ANALOG INPUTS—SHA MODE
Figure 12 shows the analog input configuration for the SHA
mode of operation. Figure 13 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential
output voltage representing the difference between the sampled
input voltage and the OFFSET voltage. The input clamp is
disabled during SHA mode operation.
AD9822
S1
2pF
S3
CML
VINR
INPUT SIGNAL
S2
2pF
CML
OFFSET
RED
VING
GREEN
VINB
BLUE
OPTIONAL DC OFFSET
(OR CONNECT TO GND)
Figure 12. SHA Mode Input Configuration (All Three Channels are Identical)
CDSCLK2
Q3
(INTERNAL)
S1, S2 CLOSED
S1, S2 CLOSED
S3 CLOSED
S3 CLOSED
S3 OPEN
S1, S2 OPEN
Figure 13. SHA Mode Internal Switch Timing
Figure 14 shows how the OFFSET pin may be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET
pin, the CIS signal is restored to 0. After the large dc offset is
removed, the signal can be scaled using the PGA to maximize
the ADC’s dynamic range.
AD9822
OFFSET
RED-OFFSET
GREEN-OFFSET
BLUE-OFFSET
VINR
VING
VINB
RED
GREEN
BLUE
0.1
µF
AVDD
VREF FROM
CIS MODULE
DC OFFSET
R1
R2
SHA
SHA
SHA
Figure 14. SHA Mode Used with External DC Offset
PROGRAMMABLE GAIN AMPLIFIERS (PGA)
The AD9822 uses one PGA for each channel. Each PGA has a
gain range from 1× (0 dB) to 5.8× (15.5 dB), adjustable in
64 steps. Figure 15 shows the PGA gain as a function of the
PGA register code. Although the gain curve is approximately
linear-in-dB, the gain in V/V varies nonlinearly with register
code, following the equation
⎥⎦
⎤
⎢⎣
⎡
−
+
=
63
63
4.7
1
5.7
G
Gain
where G is the decimal value of the gain register contents and
varies from 0 to 63.
1.0
5.7
4.0
5.0
2.0
3.0
PGA REGISTER VALUE (Decimal)
63
0
4
8
121620 2428 323640 444852 5660
15
12
9
6
3
0
Figure 15. PGA Gain Transfer Function



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