AD9773BSVZRL datasheet(27/60 Pages) AD

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AD9773

Rev. D | Page 27 of 60

CLOCK INPUT CONFIGURATIONS

The clock inputs to the AD9773 can be driven differentially or

single-ended. The internal clock circuitry has supply and

ground (CLKVDD, CLKGND) separate from the other supplies

on the chip to minimize jitter from internal noise sources.

Figure 43 shows the AD9773 driven from a single-ended clock

source. The CLK+/CLK− pins form a differential input

(CLKIN) so that the statically terminated input must be dc-

biased to the midswing voltage level of the clock driven input.

AD9773

RSERIES

CLK+

CLK–

0.1

μF

CLKVDD

CLKGND

VTHRESHOLD

Figure 43. Single-Ended Clock Driving Clock Inputs

A configuration for differentially driving the clock inputs is

given in Figure 44. DC-blocking capacitors can be used to

couple a clock driver output whose voltage swings exceed

CLKVDD or CLKGND. If the driver voltage swings are within

the supply range of the AD9773, the dc-blocking capacitors and

bias resistors are not necessary.

AD9773

CLK+

0.1

μF

0.1

μF

0.1

μF

ECL/PECL

CLK–

CLKVDD

CLKGND

Figure 44. Differential Clock Driving Clock Inputs

A transformer, such as the T1-1T from Mini-Circuits®, can also be

used to convert a single-ended clock to differential. This method is

used on the AD9773 evaluation board so that an external sine wave

with no dc offset can be used as a differential clock.

PECL/ECL drivers require varying termination networks, the

details of which are left out of Figure 43 and Figure 44 but can

be found in application notes such as the AND8020/D from On

Semiconductor®.

These networks depend on the assumed transmission line

impedance and power supply voltage of the clock driver.

Optimum performance of the AD9773 is achieved when the

driver is placed very close to the AD9773 clock inputs, thereby

negating any transmission line effects such as reflections due to

mismatch.

The quality of the clock and data input signals is important in

achieving optimum performance. The external clock driver

circuitry should provide the AD9773 with a low jitter clock

input that meets the minimum/maximum logic levels while

providing fast edges. Although fast clock edges help minimize

any jitter that manifests itself as phase noise on a reconstructed

waveform, the high gain bandwidth product of the AD9773’s

clock input comparator can tolerate differential sine wave inputs

as low as 0.5 V p-p, with minimal degradation of the output

noise floor.

PROGRAMMABLE PLL

CLKIN can function either as an input data rate clock (PLL

enabled) or as a DAC data rate clock (PLL disabled) according

to the state of Address 02h, Bit 7 in the SPI port register. The

internal operation of the AD9773 clock circuitry in these two

modes is illustrated in Figure 45 and Figure 46.

The PLL clock multiplier and distribution circuitry produce the

necessary internal synchronized 1×, 2×, 4×, and 8× clocks for

the rising edge triggered latches, interpolation filters, modu-

lators, and DACs. This circuitry consists of a phase detector,

charge pump, voltage controlled oscillator (VCO), prescaler,

clock distribution, and SPI port control. The charge pump,

VCO, differential clock input buffer, phase detector, prescaler,

and clock distribution are all powered from CLKVDD. PLL lock

status is indicated by the logic signal at the DATACLK_PLL_LOCK

pin, as well as by the status of Bit 1, Register 00h. To ensure

optimum phase noise performance from the PLL clock

multiplier and distribution, CLKVDD should originate from a

clean analog supply. The VCO speed is a function of the input

data rate, the interpolation rate, and the VCO prescaler,

according to the following function:

(

)

()

escaler

Rate

ion

Interpolat

MHz

Rate

Data

Input

MHz

Speed

VCO

Table 16 defines the minimum input data rates vs. the

interpolation and PLL divider setting. If the input data rate

drops below the defined minimum rates under these

conditions, VCO phase noise may increase significantly.

AD9773BSVZRL Datasheet(PDF) 27 Page - Analog Devices

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