MPC8248VR datasheet(17/61 Pages) FREESCALE

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MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Power Dissipation

4.7

References

Semiconductor Equipment and Materials International(415) 964-5111

805 East Middlefield Rd.

Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) Specifications800-854-7179 or

(Available from Global Engineering Documents)303-397-7956

JEDEC Specifications

http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance

and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.

212–220.

Power Dissipation

This table provides preliminary, estimated power dissipation for various configurations. Note that suitable

thermal management is required to ensure the junction temperature does not exceed the maximum

specified value. Also note that the I/O power should be included when determining whether to use a heat

sink. For a complete list of possible clock configurations, see Section 7, “Clock Configuration Modes.”

Table 8. Estimated Power Dissipation for Various Configurations1

1 Test temperature = 105° C

Bus

(MHz)

CPM

Multiplication

Factor

CPM

(MHz)

CPU

Multiplication

Factor

CPU

(MHz)

PINT(W)

2,3

2 P

INT = IDD x VDD Watts

3 Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

66.7 MHz = 0.35 W (nominal), 0.4 W (maximum)

83.3 MHz = 0.4 W (nominal), 0.5 W (maximum)

100 MHz = 0.5 W (nominal), 0.6 W (maximum)

133 MHz = 0.7 W (nominal), 0.8 W (maximum)

Vddl 1.5 Volts

Nominal

Maximum

66.67

200

266

1.2

100

200

300

1.1

1.3

100

200

400

1.3

1.5

133

267

400

1.5

1.8

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