AD7482ASTZ datasheet(16/20 Pages) AD

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AD7482

Rev. B | Page 16 of 20

Data must not be read from the AD7482 while a conversion is

taking place. For this reason, if operating the AD7482 at through-

put speeds greater than 2.5 MSPS, it is necessary to tie both the

CS pin and RD pins on the AD7482 low and use a buffer on the

data lines. This situation may also arise in the case where a read

operation cannot be completed in the time after the end of one

conversion and the start of the quiet period before the next

conversion.

The maximum slew rate at the input of the ADC must be limited to

500 V/µs while BUSY is low to avoid corrupting the ongoing

conversion. In any multiplexed application where the channel is

switched during conversion, this is to happen as soon as possible

after the

Reading Data from the AD7482

BUSY falling edge.

Data is read from the part via a 13-bit parallel data bus with the

standard CS signal and RD signal. The CS signal and

The data lines D0 to D12 leave their high impedance state when

both the

RD signal are

internally gated to enable the conversion result onto the data bus.

CS and RD are logic low. Therefore, CS may be perma-

nently tied logic low if required, and the

Figure 29

RD signal may be used

to access the conversion result.

shows a timing specifica-

tion called tQUIET. This is the amount of time that must be left

after any data bus activity before the next conversion is initiated.

Writing to the AD7482

The AD7482 features a user accessible offset register. This allows

the bottom of the transfer function to be shifted by ±200 mV. This

feature is explained in more detail in the Offset/Overrange section.

To write to the offset register, a 13-bit word is written to the

AD7482 with the 10 LSBs containing the offset value in twos

complement format. The 3 MSBs must be set to 0. The offset

value must be within the range −327 to +327, corresponding to

an offset from −200 mV to +200 mV. The value written to the

offset register is stored and used until power is removed from

the device, or the device is reset. The value stored can be updated at

any time between conversions by another write to the device.

Table 9 shows examples of offset register values and their effective

offset voltage. Figure 30 shows a timing diagram for writing to

the AD7482.

Table 9. Offset Register Examples

Code

(Decimal)

D12 to D10

D9 to D0 (Twos

Complement)

Offset

(mV)

−327

000

1010111001

−200

−128

000

1110000000

−78.12

+64

000

0001000000

+39.06

+327

000

0101000111

+200

Driving the CONVST

To achieve the specified performance from the AD7482, the

CONVST pin must be driven from a low jitter source. Because

the falling edge on the

( )

(

log

JITTER

SNR

CONVST pin determines the sampling

instant, any jitter that may exist on this edge appears as noise

when the analog input signal contains high frequency components.

The relationship between the analog input frequency (fIN), timing

jitter (tj), and resulting SNR is given by

For example, if the desired SNR due to jitter was 100 dB with a

maximum full-scale analog input frequency of 1.5 MHz, ignoring

all other noise sources, the result is an allowable jitter on the

CONVST falling edge of 1.06 ps. For a 12-bit converter (ideal

SNR = 74 dB), the allowable jitter is greater than 1.06 ps, but

due consideration must be given to the design of the

Typical Connection

CONVST

circuitry to achieve 12-bit performance with large analog input

frequencies.

Figure 23 shows a typical connection diagram for the AD7482

operating in Parallel Mode 1. Conversion is initiated by a falling

edge on CONVST. When CONVST goes low, the BUSY signal

goes low, and at the end of conversion, the rising edge of BUSY

is used to activate an interrupt service routine. The CS and

lines are then activated to read the 12 data bits (13 bits if using

the overrange feature).

Figure 23, the VDRIVE pin is tied to DVDD, which results in

logic output levels being either 0 V or DVDD. The voltage applied to

VDRIVE controls the voltage value of the output logic signals. For

example, if DVDD is supplied by a 5 V supply and VDRIVE is supplied

by a 3 V supply, the logic output levels are either 0 V or 3 V. This

feature allows the AD7482 to interface to 3 V devices, while still

enabling the ADC to process signals at a 5 V supply.

RESET

PARALLEL

INTERFACE

MODE1

MODE2

WRITE

CLIP

NAP

STBY

D0 TO D12

CONVST

BUSY

CBIAS

REFSEL

REFIN

REFOUT

VIN

AD7482

ADM809

VDRIVE DVDD AVDD

0.1µF

DIGITAL

SUPPLY

4.75V TO 5.25V

10µF

1nF

0.1µF

47µF

ANALOG

SUPPLY

4.75V TO 5.25V

0V TO 2.5V

1nF

0.47µF

AD780 2.5V

REFERENCE

Figure 23. Typical Connection Diagram

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