MPC8306S datasheet(39/70 Pages) FREESCALE

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

SPI

17.2

SPI AC Timing Specifications

The following table and provide the SPI input and output AC timing specifications.

The following figure provides the AC test load for the SPI.

Figure 29. SPI AC Test Load

Figure 30 and Figure 31 represent the AC timing from Table 43. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Table 42. SPI DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

VOH

IOH = –6.0 mA

2.4

—

Output low voltage

VOL

IOL = 6.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Input high voltage

VIH

—

2.0

OVDD +0.3

Input low voltage

VIL

—–0.3

0.8

Input current

IIN

0 V

 VIN  OVDD

—

±5

A

Table 43. SPI AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

SPI outputs—Master mode (internal clock) delay

tNIKHOV

0.5

SPI outputs—Slave mode (external clock) delay

tNEKHOV

SPI inputs—Master mode (internal clock) input setup time

tNIIVKH

6—

SPI inputs—Master mode (internal clock) input hold time

tNIIXKH

0—

SPI inputs—Slave mode (external clock) input setup time

tNEIVKH

4—

SPI inputs—Slave mode (external clock) input hold time

tNEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI

outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are

valid (V).

3. All units of output delay must be enabled for 8306S output port spimosi (SPI Master Mode)

4. delay units must not be enabled for Slave Mode.

Output

Z0 = 50 

OVDD/2

RL = 50 

MPC8306S Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

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