AM3703 datasheet(64/280 Pages) TI

64 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

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(1) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full

description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical

Reference Manual (literature number SPRUGN4).

(2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior.

(3) PU = [50 to 100 k

Ω] per default or [10 to 50 kΩ] according to the selected mode.

For a full description of the pull-up drive strength programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in

the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).

PD: 30 to 150 k

Ω.

(4) These signals are feed-through balls. For more information, see Table 2-27.

(5) NA in this table stands for "Not Applicable".

(6) In the safe_mode_out1, the buffer is configured to drive 1.

(7) Depending on the sys_clkreq direction the corresponding reset released state value can be:

–

Z if sys_clkreq is used as input

–

1 if sys_clkreq is used as output

For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device

Technical Reference Manual (literature number SPRUGN4).

(8) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x

Multimedia Device Technical Reference Manual (literature number SPRUGN4).

(9) The pullup and pulldown can be either the standard LVCMOS 100-

μA drive strength or the I2C pullup and pulldown described as

follows: Nominal resistance = 1.66 k

Ω in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load

range of 5 pF to 15 pF.

(10) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive

strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1,

CONTROL_PROG_IO_WKUP1 control modules in the System Control Module chapter of the AM/DM37x Multimedia Device Technical

Reference Manual (literature number SPRUGN4) to modify the IO settings if required by the targeted interface application.

(11) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see

PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and

prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the

System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to

modify the IO settings if required by the targeted interface application.

(12) Mux0 if sys_boot6 is pulled down (clock master).

(13) If MMC1 functional signals are enabled, vdds_mmc1 for MMC1 must be supplied by a dedicated power source.

If MMC1 functional signals are disabled, other multiplexed CMOS signals of the interface can be enabled. The interface can be supplied

by the same power source as vdds. The vdds power source supplies the vdds_mmc1 ball.

If neither MMC1 functional balls or CMOS signals are enabled, the interface balls are left unconnected with its associated power supply

(vdda/vssa) grounded.

For the corresponding setting of the PBIASLITEPWRDNZ0 bit, see the System Control Module / SCM Programming Model /

Extended-Drain I/Os and PBIAS Cells Programming Guide section of the AM/DM37x Multimedia Device Technical Reference Manual

(literature number SPRUGN4).

Table 2-3. Ball Characteristics (CUS Pkg.)(1)

BALL

PIN NAME [2]

MODE [3]

TYPE [4]

BALL RESET BALL RESET RESET REL. POWER [8]

HYS [9]

BUFFER

PULLUP

IO CELL [12]

NUMBER [1]

STATE [5]

REL. STATE MODE [7]

STRENGTH

/DOWN

[6]

(mA) [10]

TYPE [11]

sdrc_d0

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

sdrc_d1

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

sdrc_d2

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

sdrc_d3

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

sdrc_d4

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

D10

sdrc_d5

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

sdrc_d6

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

sdrc_d7

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

B11

sdrc_d8

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

C12

sdrc_d9

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

B12

sdrc_d10

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

D13

sdrc_d11

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

C13

sdrc_d12

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

B14

sdrc_d13

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

A14

sdrc_d14

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

B15

sdrc_d15

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

sdrc_d16

vdds_mem

Yes

(8)

PU/ PD

LVCMOS

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