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AM3703 Datasheet(PDF) 158 Page - Texas Instruments

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Part # AM3703
Description  Sitara ARM Microprocessors
PDF  280 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3703 Datasheet(HTML) 158 Page - Texas Instruments

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SWPS038-013
Tn–1
Tn
Tn+1
AM3715, AM3703
SPRS616F
– JUNE 2010 – REVISED AUGUST 2011
www.ti.com
6
Timing Requirements and Switching Characteristics
6.1
Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
unless otherwise specified.
6.2
Interface Clock Specifications
6.2.1
Interface Clock Terminology
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly
with the interface protocol.
6.2.2
Interface Clock Frequency
The two interface clock characteristics are:
•
The maximum clock frequency
•
The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the device IC and doesn
’t take into account any system consideration (PCB,
Peripherals).
The system designer will have to consider these system considerations and the device IC timing
characteristics as well, to define properly the maximum operating frequency, which corresponds to the
maximum frequency supported to transfer the data on this interface.
6.2.3
Clock Jitter Specifications
Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this
document is the time difference between the typical cycle period and the actual cycle period affected by
noise sources on the clock. The cycle (or period) jitter terminology will be used to identify this type of jitter.
Figure 6-1. Cycle (or Period) Jitter
NOTE
Max. Cycle Jitter = Max (Ti)
Min. Cycle Jitter = Min (Ti)
Jitter Standard Deviation (or RMS Jitter) = Standard Deviation (Ti)
6.2.4
Clock Duty Cycle Error
The maximum duty cycle error is the difference between the absolute value of the maximum high-level
pulse duration or the maximum low-level pulse duration and the typical pulse duration value.
•
Maximum pulse duration = Typical pulse duration + maximum duty cycle error
•
Minimum pulse duration = Typical pulse duration - maximum duty cycle error
158
Timing Requirements and Switching Characteristics
Copyright
© 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): AM3715 AM3703



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