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AM3703CUS Datasheet(PDF) 238 Page - Texas Instruments |
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AM3703CUS Datasheet(HTML) 238 Page - Texas Instruments |
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238 / 280 page  SWPS038-084 i2cX_sda i2cX_scl START REPEAT STOP START START I1 I2 I3 I4 I5 I6 I6 I7 I8 SWPS038-085 i2cX_sda i2cX_scl STOP START REPEAT IH1 IH2 IH3 IH4 IH6 IH5 IH7 AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com (1) In i2cX, X is equal to 1, 2, 3, or 4. Figure 6-53. I2C —Standard and Fast Modes 6.6.5.2 I2C —High-Speed Mode Table 6-98. I2C —High-Speed Mode NO. PARAMETER MIN MAX UNIT fscl Frequency, clock i2cx_scl(3) 3.4(5) MHz I1 tw(sclH) Pulse duration, clock i2cx_scl(3) high 60(1) ns I2 tw(sclL) Pulse duration, clock i2cx_scl(3) low 160(1) ns I3 tsu(sdaV-sclH) Setup time, data i2cx_sda(3) valid before clock i2cx_scl(3) active level 10 ns I4 th(sclH-sdaV) Hold time, data i2cx_sda(3) valid after clock i2cx_scl(3) active level 0(4) 70 ns I5 tsu(sdaL-sclH) Setup time, clock i2cx_scl(3) high after data i2cx_sda(3) low (for a 160 ns START(2) condition or a repeated START condition) I6 th(sclH-sdaH) Hold time, data i2cx_sda(3) low level after clock i2cx_scl(3) high level 160 ns (STOP condition) I7 th(sclH-RSTART) Hold time, data i2cx_sda(3) low level after clock i2cx_scl(3) high level 160 ns (for a repeated START condition) tR(scl) Rise time, clock i2cx_scl(3) 10 40 ns tR(scl) Rise time, clock i2cx_scl(3) after a repeated START condition and after 10 80 ns a bit acknowledge tF(scl) Fall time, clock i2cx_scl(3) 10 40 ns tR(sda) Rise time, data i2cx_sda(3) 10 80 ns tF(sda) Fall time, data i2cx_sda(3) 10 80 ns CB Capacitive load for each bus line 100 pF (1) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(sclL) > 2 * tw(sclH). (2) After this time, the first clock is generated. (3) In i2cx, x is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only. (4) The device provides (via the I2C bus) a minimum hold time (= I2C_FCLK period x 4) for the i2cx_sda(3) signal (see the fall and rise times of i2cx_scl(3)) to bridge the undefined region of the falling edge of i2cx_scl(3). (5) The I2C4 clock frequency in high-speed mode is equal to the sys_xtalin input clock frequency divided by 15. (1) In i2cX, X is equal to 1, 2, 3, or 4. Figure 6-54. I2C —High-Speed Mode 238 Timing Requirements and Switching Characteristics Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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