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Data Sheet

AD9235

Rev. D | Page 19 of 40

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or to improve thermal drift

characteristics. When multiple ADCs track one another, a single

reference (internal or external) may be necessary to reduce gain

matching errors to an acceptable level. A high precision external

reference may also be selected to provide lower gain and offset

temperature drift. Figure 41 shows the typical drift characteris-

tics of the internal reference in both 1 V and 0.5 V modes.

TEMPERATURE (°C)

–40 –30 –20 –10

1.2

1.0

0.8

0.6

0.4

0.2

VREF = 1.0V

VREF = 0.5V

Figure 41. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 1 V.

If the internal reference of the AD9235 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 42

depicts how the internal reference voltage is affected by loading.

LOAD (mA)

3.0

0.5

1.0

1.5

2.0

2.5

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

0.5V ERROR (%)

1V ERROR (%)

Figure 42. VREF Accuracy vs. Load

OPERATIONAL MODE SELECTION

As discussed earlier, the AD9235 can output data in either offset

binary or twos complement format. There is also a provision for

enabling or disabling the clock DCS. The MODE pin is a multi-

level input that controls the data format and DCS state. The

input threshold values and corresponding mode selections are

outlined in Table 8.

Table 8. Mode Selection

MODE Voltage

Data Format

Duty Cycle Stabilizer

AVDD

Twos Complement

Disabled

2/3 AVDD

Twos Complement

Enabled

1/3 AVDD

Offset Binary

Enabled

AGND (Default)

Offset Binary

Disabled

The MODE pin is internally pulled down to AGND by a 20 kΩ

resistor.

TSSOP EVALUATION BOARD

The AD9235 evaluation board provides the support circuitry

required to operate the ADC in its various modes and configu-

rations. The converter can be driven differentially, through an

AD8138 driver or a transformer, or single-ended. Separate pow-

er pins are provided to isolate the DUT from the support cir-

cuitry. Each input configuration can be selected by proper con-

nection of various jumpers (refer to the schematics). Figure 43

shows the typical bench characterization setup used to evaluate

the ac performance of the AD9235. It is critical that signal

sources with very low phase noise (<1 ps rms jitter) be used to

realize the ultimate performance of the converter. Proper filter-

ing of the input signal, to remove harmonics and lower the inte-

grated noise at the input, is also necessary to achieve the speci-

fied noise performance.

The AUXCLK input should be selected in applications requiring

the lowest jitter and SNR performance, i.e., IF undersampling

characterization. It allows the user to apply a clock input signal

that is 4× the target sample rate of the AD9235. A low-jitter,

differential divide-by-4 counter, the MC100LVEL33D, provides

a 1× clock output that is subsequently returned back to the CLK

input via JP9. For example, a 260 MHz signal (sinusoid) is

divided down to a 65 MHz signal for clocking the ADC. Note

that R1 must be removed with the AUXCLK interface. Lower

jitter is often achieved with this interface since many RF signal

generators display improved phase noise at higher output

frequencies and the slew rate of the sinusoidal output signal is

4× that of a 1× signal of equal amplitude.

Complete schematics and layout plots follow and demonstrate

the proper routing and grounding techniques that should be

applied at the system level.

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