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AD1954

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BYTE 0

BYTE 1

BYTE 4

CDATA

CCLK

CLATCH

Figure 16. Sample of SPI Write Format (Single-Write Mode)

BYTE 0

CDATA

CCLK

CLATCH

COUT

BYTE 1

HI-Z

DATA

XXX

DATA

HI-Z

SPI PORT

Overview

The AD1954 has many different control options. Most signal

processing parameters are controlled by writing new values to

the parameter RAM using the SPI port. Other functions, such as

volume and de-emphasis filtering, are programmed by writing to

the SPI control registers.

The SPI port uses a 4-wire interface, consisting of CLATCH,

CCLK, CDATA, and COUT signals.The CLATCH signal goes

low at the beginning of a transaction and high at the end of a

transaction.The CCLK signal latches the serial input data on a

low-to-high transition.The CDATA signal carries the serial input

data, and the COUT signal is the serial output data.The COUT

signal remains three-stated until a read operation is requested.

This allows other SPI compatible peripherals to share the same

readback line.

The SPI port is capable of full read/write operation for all of the

memories (parameter and program) and some of the SPI registers

(Control Register 1 and the data capture registers).The memories

may be accessed in both a single address mode or in burst mode.

All SPI transactions follow the same basic format that is shown in

Table I.

Table I. SPI Word Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

00000, R/W

00000, R/

00000, R/ , Addr[9:8] Addr[7:0] Data

Data

The R/W

The R/

bit is low for a write and high for a read operation.

The 10-bit address word is decoded into either a location in one

of the two memories (parameter or program) or one of the SPI

registers.The number of data bytes varies according to the regis-

ter or memory being accessed. In burst-write mode (available for

loading the RAMs only), an initial address is given followed by a

continuous sequence of data for consecutive RAM locations.The

detailed data format diagram for continuous-mode operation is

given in SPI read/write data formats.

A sample timing diagram for a single SPI write operation to the

parameter RAM is shown in Figure 16.

A sample timing diagram of a single SPI read operation is shown

in Figure 17.The COUT pin goes from three-state to driven at

the beginning of Byte 2. Bytes 0 and 1 contain the address and

R/W

bit, and Bytes 2 through 4 carry the data.The exact format

is shown in Tables VIII to XIX.

The AD1954 has several mechanisms for updating signal-processing

parameters in real time without causing loud pops or clicks. In

cases where large blocks of data need to be downloaded, the DSP

core can be shut down and new data loaded, and then the core

can be restarted.The shutdown and restart mechanisms employ a

gradual volume ramp to prevent clicks and pops. In cases where

only a few parameters need to be changed (e.g., a single biquad

filter), a safeload mechanism is used, which allows a block of SPI

registers to be transferred to the parameter RAM within a single

audio frame while the core is running.The safeload mode uses

internal logic to prevent contention between the DSP core and

the SPI port.

REV. A

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