AD5545 datasheet(6/25 Pages) AD

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AD5405

Rev. B | Page 5 of 24

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,

VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter1

Limit at TMIN, TMAX

Unit

Conditions/Comments

Write Mode

ns min

R/W-to-CS setup time

ns min

R/W-to-CS hold time

ns min

CS low time

ns min

Address setup time

ns min

Address hold time

ns min

Data setup time

ns min

Data hold time

ns min

R/W high to CS low

ns min

CS min high time

t14

ns typ

CS rising-to-LDAC falling time

t15

ns typ

LDAC pulse width

t16

ns typ

CS rising-to-LDAC rising time

t17

ns typ

LDAC falling-to-CS rising time

Data Readback Mode

t10

ns typ

Address setup time

t11

ns typ

Address hold time

t12

ns typ

Data access time

ns max

t13

ns typ

Bus relinquish time

ns max

Update Rate

21.3

MSPS

Consists of CS min high time, CS low time, and output voltage settling time

1 Guaranteed by design and characterization, not subject to production test.

DATA VALID

R/W

DATA

t13

t12

DACA/DACB

t11

t10

LDAC2

LDAC1

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

t16

t14

t15

t17

DATA VALID

Figure 2. Timing Diagram

IOL

200

μA

IOH

200

μA

50pF

OUTPUT

VOH (MIN) + VOL (MAX)

Figure 3. Load Circuit for Data Timing Specifications

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