AD79821 datasheet(16/24 Pages) AD

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AD7946

Rev. A | Page 16 of 24

AD7946

REF

GND

VDD

IN–

IN+

VIO

SDI

SCK

SDO

CNV

100nF

10µF

ADR364

33Ω

2.7nF

0V TO 4.096V

ADA4841

100nF

>5.2V

100nF

Figure 32. Example of a Single-Supply Application Circuit

DIGITAL INTERFACE

Although the AD7946 has a reduced number of pins, it offers

flexibility in its serial interface modes.

The AD7946, when in CS mode, is compatible with SPI, QSPI™,

digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or

ADSP-219x. This interface can use either 3-wire or 4-wire. A

3-wire interface using the CNV, SCK, and SDO signals mini-

mizes wiring connections useful, for instance, in isolated

applications. A 4-wire interface using the SDI, CNV, SCK, and

SDO signals allows CNV, which initiates the conversions, to be

independent of the readback timing (SDI). This is useful in low

jitter sampling or simultaneous sampling applications.

The AD7946, when in chain mode, provides a daisy chain

feature using the SDI input for cascading multiple ADCs on a

single data line similar to a shift register.

The operating mode depends on the SDI level when the CNV

rising edge occurs. CS mode is selected if SDI is high, and chain

mode is selected if SDI is low. The SDI hold time is such that

when SDI and CNV are connected, the chain mode is always

selected.

In either mode, the AD7946 offers the flexibility to optionally

force a start bit in front of the data bits. This start bit can be

used as a BUSY signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a BUSY indicator,

the user must time out the maximum conversion time prior to

readback.

BUSY indicator feature is enabled

•

In CS mode, if CNV or SDI is low when the ADC

conversion ends (see Figure 36 and Figure 40).

•

In chain mode, if SCK is high during the CNV rising edge

(see Figure 44).

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