SIC413DB datasheet(13/18 Pages) VISHAY

13 / 18 page

Vishay Siliconix

SiC413

Document Number: 69057

S09-2250-Rev. D, 26-Oct-09

www.vishay.com

PCB Layout

As in the design of any switching dc-to-dc converter, a good

PCB layout ensures successful transition from design to

production. One of a few drawbacks of switching converters

is the noise generated by the high frequency switching and

coupled by parasitic inductance and capacitance. However,

noise levels can be reduced or minimized if a PCB is well laid

out.

The following is a guidance on SiC413 layout.

Input Capacitors: C1 through to C6 are the input capacitors.

They are placed side by side together to form a block and this

block sits right beside SiC413's VIN and GND pins. This

placement minimizes the distance between VIN pin,

capacitors and chip’s ground, which minimizes the possibility

of noise injected in VIN pin.

Also the MLCC with smallest value (0.01 µF) is placed

closest to VIN pin, and then MLCC with larger values (0.1 µF,

10 µF) and the last, the electrolytic. This is because their

ESRs are getting larger and larger from small value MLCC to

large value MLCC and then electrolytic capacitor.

Output Capacitors: C17 through to C20 are the output

capacitors. They are placed the same way as input

capacitors.

Decoupling Capacitors of VREG: C7 and C8, are placed right

beside GND pin on their negative sides. Their positive sides

are connected to the chip's VREG pin through two vias from

the bottom of the PCB. The trace distance should be kept

less than 10 mm.

Boot Capacitor: C14 is the boot capacitor. R5 is added to

allow flexibility for adjusting the high-side MOSFET driving

current to reduce possible noise.

Compensation Network: C9, C10, R6 and R10 form this

network. These components should be placed in a tight

group. This group then should be in close proximity to the

COMP pin. Trace lengths between the components should

be minimized.

Output Sampling Network: R7, C15, R9 and R11 constitute

the output voltage sampling network. These components

should be placed in a tight grouping and in close proximity to

the FB pin. Since SiC413 has only one GND pin, this makes

the chip more sensitive to noise coming from GND.

Therefore R11 is added to perform as a filter to remove any

possible noise from ground.

Grounding: Separate analog and power ground paths are

recommended for optimal noise reduction in the SiC413CB

converter. These grounds should both be connected at the

GND pin. Connect the ground pin of the input and output

capacitors to the power ground. Connect the ground pin for

the VREG decoupling caps, the compensation network

grounds, and the output voltage sampling network grounds

to the analog ground. It is preferred to use low inductance

ground planes when ever possible. If single sided board is

being used then try to keep the ground traces short and

going a star configuration at the GND pin.

Power Traces: The power path is formed starting at VIN. It

then branches to PGND and VSW to VOUT. The trace

thickness for the power path should be kept to a minimum of

50 mils. Placement of components should focus on keeping

these traces as short as possible to minimize parasitic

inductance and resistances. They have minimum 50 mil

trace width (at the VIN pin area) and this segment is very

short, which is good enough for the power level handled by

this chip.

Figure 6 and Figure 7 below show a recommended board

layout for converters using SiC413CB.

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