1.22V

25 PA

-

1.22V

,

1.1V

25 PA

-

1.1V

,

CSG

CS

LO

RAMP

1k

1k

+

-

10k

10k

0.5V

1.6V

CURRENT LIMIT

COMPARATOR

CURRENT SENSE

AMPLIFIER

A =

10k

-

+

-

+

HO

LM5116

www.ti.com

SNVS499G – FEBRUARY 2007 – REVISED MARCH 2013

comparator. If an overshoot should occur, the sample-and-hold circuit will detect the excess recirculating current.

If the sample-and-hold DC level exceeds the internal current limit threshold, the buck switch will be disabled and

skip pulses until the current has decayed below the current limit threshold. This approach prevents current

runaway conditions due to propagation delays or inductor saturation since the inductor current is forced to decay

following any current overshoot.

Figure 33. Current Limit and Ramp Circuit

Using a current sense resistor in the source of the low-side MOSFET provides superior current limit accuracy

with temperature and part-to-part variation. The CS and CSG pins should be Kelvin connected to the current

sense resistor or MOSFET drain and source.

The peak current which triggers the current limit comparator is:

where

•

(5)

The 1.1V threshold is the difference between the 1.6V reference at the current limit comparator and the 0.5V

offset at the current sense amplifier. This offset at the current sense amplifier allows the inductor ripple current to

Current limit hysteresis prevents chatter around the threshold when VCCX is powered from VOUT. When 4.5V <

VCC < 5.8V, the 1.6V reference is increased to 1.72V. The peak current which triggers the current limit

comparator becomes:

(6)

This has the effect of a 10% fold-back of the peak current during a short circuit when VCCX is powered from a

5V output.

Soft-Start and Diode Emulation

The soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing

start-up stresses and surges. The LM5116 will regulate the FB pin to the SS pin voltage or the internal 1.215V

reference, whichever is lower. At the beginning of the soft-start sequence when SS = 0V, the internal 10 µA soft-

pin resulting in a gradual rise of FB and the output voltage.

Copyright © 2007–2013, Texas Instruments Incorporated

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