48GA004 datasheet(210/268 Pages) MICROCHIP

210 / 268 page

PIC24FJ64GA004 FAMILY

DS39881D-page 210

 2010 Microchip Technology Inc.

CW2: FLASH CONFIGURATION WORD 2

U-1

—

bit 23

bit 16

R/PO-1

IESO

WUTSEL1(1) WUTSEL0(1) SOSCSEL1(1) SOSCSEL0(1)

FNOSC2

FNOSC1

FNOSC0

bit 15

bit 8

R/PO-1

U-1

R/PO-1

FCKSM1

FCKSM0

OSCIOFCN

IOL1WAY

—

I2C1SEL

POSCMD1

POSCMD0

bit 7

bit 0

Legend:

r = Reserved bit

R = Readable bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 23-16

Unimplemented:

Read as ‘1’

bit 15

IESO:

Internal External Switchover bit

= IESO mode (Two-Speed Start-up) enabled

= IESO mode (Two-Speed Start-up) disabled

bit 14-13

WUTSEL1:WUTSEL0:

Voltage Regulator Standby Mode Wake-up Time Select bits(1)

= Default regulator start-up time used

= Fast regulator start-up time used

= Reserved; do not use

bit 12-11

SOSCSEL1:SOSCSEL0:

Secondary Oscillator Power Mode Select bits(1)

= Default (High Drive Strength) mode

= Low-Power (Low Drive Strength) mode

= Reserved; do not use

bit 10-8

FNOSC2:FNOSC0:

Initial Oscillator Select bits

111

= Fast RC Oscillator with Postscaler (FRCDIV)

110

= Reserved

101

= Low-Power RC Oscillator (LPRC)

100

= Secondary Oscillator (SOSC)

011

= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010

= Primary Oscillator (XT, HS, EC)

001

= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000

= Fast RC Oscillator (FRC)

bit 7-6

FCKSM1:FCKSM0:

Clock Switching and Fail-Safe Clock Monitor Configuration bits

= Clock switching and Fail-Safe Clock Monitor are disabled

= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

bit 5

OSCIOFCN:

OSCO Pin Configuration bit

If POSCMD1:POSCMD0 = 11 or 00:

= OSCO/CLKO/RA3 functions as CLKO (FOSC/2)

= OSCO/CLKO/RA3 functions as port I/O (RA3)

If POSCMD1:POSCMD0 = 10 or 01:

OSCIOFCN has no effect on OSCO/CLKO/RA3.

bit 4

IOL1WAY:

IOLOCK One-Way Set Enable bit

= The OSCCON<IOLOCK> bit can be set once, provided the unlock sequence has been completed.

Once set, the Peripheral Pin Select registers cannot be written to a second time.

= The OSCCON<IOLOCK> bit can be set and cleared as needed, provided the unlock sequence has

been completed

bit 3

Unimplemented:

Read as ‘1’

48GA004 Datasheet(PDF) 210 Page - Microchip Technology

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