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PCM1750UG4 Datasheet(PDF) 6 Page - Texas Instruments |
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PCM1750UG4 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 21 page  ® PCM1750 6 25k 25k 150k 5k 5k 12a 3b 3a 2b 1b 1a 2T 1T 3T 12T off S C V REF P16, P27 +V (+5V) P15, P28 .01µF P19, P24 500 13.25k A1 A2 Latch Comparator Data Out AZ CAZ (MSB) S V C 10PF 1 2 3 IN REF 5PF 20PF 1 L V S S 3 C2 C1 1 CAZ2 AZ2 AZ CAZ 3 3 CAZ4 AZ4 47k A .01µF +V (+5V) A off C Roffb 500 R 12b R S 12T R R R S 3T C S 2T C S 1T C R R a b R R Ω Ω Ω Ω Ω Ω Ω 2a R Ω Ω 100mV H1 H2 P18, P25 V Simplified V Circuit REFIN REFIN +V (+5V) A 917 Ω P18, P25 V REFIN Roffa 47k Ω V REFOUT Optional External Adjustment Circuitry TDAC Auto-Zeroed Comparator CDAC 0 to 120pF (Code dependent) MSB Adj Off Adj = 2.75V 600 Ω 13.25k Ω THEORY OF OPERATION OVERVIEW The PCM1750 is a dual 18-bit successive approximation CMOS analog-to-digital converter with serial data outputs designed especially for digital audio and similar applica- tions. The single-chip converter is fabricated on a 3 µ P-well CMOS process which includes poly-poly capacitors, laser- trimmable nichrome resistors, and two layers of interconnect metal. The dual converter employs a switched capacitor architecture which provides separate, simultaneous S/H (sample/hold) functions for each input channel. The separate S/H for each channel results in a desired feature called co-phase sampling which means that both S/H circuits are switched at the same time into the HOLD mode to capture their respective input signals simultaneously. This elimi- nates phasing errors produced by alternative architecture ADCs which do not sample the two input channels at the same time. Switched binary-weighted poly-poly capacitors are used in CDAC (capacitive digital-to-analog converter) configura- tions to form the successive approximation converter sec- FIGURE 1. PCM1750 Simplified Circuit Diagram. |
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