TC253SPD

680×500 PIXEL CCD IMAGE SENSOR

SOCS062B – JANUARY 2001 – REVISED MAY 2002

14

POST OFFICE BOX 655303

SRG1

SRG2

V

S/H

Clamp

CMG

Reset Level

OUT1,2

{ Output signal may not be zero for zero-input charge. Offset level up to 100 mV may be present.

Output Signal{

Figure 5. Detail Serial Register Clock Timing for CDS Implementation