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AD9961/AD9963

Data Sheet

Rev. A | Page 50 of 60

The Tx port has an optional double data rate (DDR) clock

mode. In DDR mode, the transmit data is latched on both the

rising and falling edges of TXCLK. The polarity of the edge

identifies to which channel the input data is intended. In this

mode, the TXIQ signal is not required.

The interleaved digital data for the I and Q DACs is accepted by

the Tx bus (TXD([11:0]). The data must be presented to the

device such that it is stable throughout the setup and hold

times, tS and tH, around both the rising and falling edges of the

TXCLK signal. A detailed timing diagram is shown in Figure 81.

TXD[11:0]

TXCLK

tSU

tHD

tSU

tHD

Figure 81. Tx Port Timing Diagram (DDR Clock Mode)

In DDR mode, the TXCLK signal is always an input and must

be supplied along with the data. The setup and hold time

requirements for the Tx port in DDR mode are given Table 24

Table 24. Tx Port Setup and Hold Times From −40°C to

+85°C1

Tx Port

Operating Mode

DRVDD = 1.8 V

DRVDD = 3.3 V

tSU

(Min)

tHD

(Min)

tSU

(Min)

tHD

(Min)

Unit

TXCLK_MD = 01

−0.02

+2.60

+0.29

+1.99

TXCLK_MD = 10,

TXDBLSEL = 1

−1.04

+4.24

−0.28

+3.92

TXCLK_MD = 10,

TXDBLSEL = 0

−0.61

+4.76

−0.14

+4.82

1 Specifications are preliminary and subject to change.

The input samples to the device are assembled to create a

quadrature pair of data. The two possible data pairing orders

and two possible data to TXIQ signal phase relationships create

four possible timing modes. The AD9961/AD9963 can be

configured to accept data in any of these four modes. The data

pairing order is controlled by the TX_IFIRST bit. The data to

TXIQ phase relationship is controlled by the TXIQ_HILO bit.

The two programming options produce the four timing

diagrams shown in Figure 82.

TXCLK

TXD[11 :0]

TXIFIRST = 1

TXIQPH = 1

TXIFIRST = 1

TXIQPH = 0

TXIFIRST = 0

TXIQPH = 1

TXIFIRST = 0

TXIQPH = 0

Figure 82. Transmit Path Timing Modes (DDR Mode)

HALF-DUPLEX MODE

The AD9961/AD9963 offer a half-duplex mode enabling a

reduced width digital interface. In half-duplex mode, the

transmit and receive ports are multiplexed onto the TRXD,

TRXIQ, and TRXCLK lines. The direction of the bus can be

controlled by either the TXIQ/TXnRX pin (for the rest of this

section referred to as simply the TXnRX pin) or the serial port

configuration registers.

The operation of the transmit and receive ports in half-duplex

mode is very similar to the way they operate in full-duplex

mode. In half-duplex mode, the interface can be configured to

operate with a single clock pin, or with two clock pins. When in

Rx mode (sourcing data) the TRX port operates the same in

half-duplex mode as it does in full duplex. When in Tx mode,

the TXIQ and TXD[11:0] signals are mapped onto the TRXIQ

and TRXD[11:0] pins respectively. The TXCLK pin is mapped

to the TRXCLK pin in one-clock mode and remains on the

TXCLK pin in two-clock mode. Therefore, in one-clock mode,

the TRXCLK pin carries the RXCLK signal when set in the Rx

direction and the TXCLK signal when set in the Tx direction.

In two-clock mode, the TRX pin carries the RXCLK signal and

the TXCLK pin carries the TXCLK signal regardless of the bus

direction. By default, the clocks sourced by the device are only

present when the corresponding direction of the bus is active.

Setup and hold times for the TRx port are shown in Table 25.

Table 25. TRx Port Setup and Hold Times From −40°C to

+85°C

TRx Port

Operating Mode

DRVDD = 1.8 V

DRVDD = 3.3 V

tSU

(Min)

tHD

(Min)

tSU

(Min)

tHD

(Min)

Units

TXCLK_MD = 01

+0.73

+1.61

+0.44

+1.90

TXCLK_MD = 10,

TXDBLSEL = 1

−1.66

+5.84

−0.96

+4.55

TXCLK_MD = 10,

TXDBLSEL = 0

−1.40

+6.62

−1.15

+5.11

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