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LNBH26PQR Datasheet(PDF) 6 Page - STMicroelectronics

Part # LNBH26PQR
Description  Dual LNBS supply and control IC with step-up and I짼C interface
PDF  38 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LNBH26PQR Datasheet(HTML) 6 Page - STMicroelectronics

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Application information (valid for each section A/B)
LNBH26
6/38
Doc ID 022771 Rev 1
Figure 2.
Tone enable and disable timing (using external waveform)
2.3
Data encoding by external DiSEqC envelope control through
the DSQIN pin
If an external DiSEqC™ envelope source is available, it is possible to use the internal 22
kHz generator activated during the tone transmission by connecting the DiSEqC™ envelope
source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and
TEN=1. In this way the internal 22 kHz signal is superimposed on the VOUT DC voltage to
generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH
the internal control circuit activates the 22 kHz tone output.
The 22 kHz tone on the VOUT pin is activated with a delay of about 6 µs from DSQIN TTL
signal rising edge, and it stops with a delay time in the range of 15 µs to 60 µs after the 22
kHz TTL signal on DSQIN has expired (refer to
Figure 3).
Figure 3.
Tone enable and disable timing (using envelope signal)
2.4
LPM (low power mode)
In order to reduce total power loss, each section of the LNBH26 is provided with the LPM I²C
bit that can be activated (LPM=1) in applications where the 22 kHz tone can be disabled for
long time periods. The LPM bit can be set to “1” when the DiSEqC™ data transmission is
not requested (no 22 kHz tone output is present); in this condition the drop voltage across
the integrated LDO regulator (VUP - VOUT) is reduced to 0.6 V typ. and, consequently, the
power loss inside the relative LNBH26 channel regulator is reduced too. For example, at 500
mA load, LPM=1, allowing a minimum LDO dissipated power of 0.3 W typ. It is
recommended to set the LPM bit to “0” before starting the 22 kHz DiSEqC™ data
transmission; in this condition the drop voltage across the LDO is kept to 1 V typ. Keep
LPM=0 at all times in case the LPM function is not used.
2.5
DISEQC™ 2.0 implementation
The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC™ 2.0 interfacing.
Each LNBH26 section DETIN pin must be AC coupled to the DiSEqC™ bus, and extracted
PWK data is available on the corresponding DSQOUT pin. To comply with the bi-directional
DiSEqC™ 2.0 bus hardware requirements, an output R-L filter is needed (per each voltage
AM10426v1
~ 1 µs
~ 60 µs
DSQIN
Tone
Output
AM10427v1
~ 6 µs
15 µs ~ 60 µs
DSQIN
Tone
Output



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