QUICC

MASTER

QUICC

SLAVE

CPU32+

QUICC SYSTEM BUS

SCC

SCC

SCC

SCC

SMC

SMC

SPI

SCC

SCC

SCC

SCC

SMC

SMC

SPI

CPU32+

Figure 8. Master-Slave QUICC Implementation

The QUICC has special features in slave mode to support the M68040 family. When the QUICC is used in

this way, it is said to be in MC68040 companion mode. Figure 9 shows how a QUICC in slave mode can

interface to a MC68EC040. (The MC68EC040 is a low-cost version of the MC68040 with identical integer

performance, but without the memory management unit (MMU) and the floating-point unit (FPU).) The DRAM

controller on the QUICC will control the accesses of the MC68EC040 (including the burst modes). This

configuration does require external address mutiplexers, but the QUICC controls the multiplexers. The

QUICC supports the MC68EC040 in other ways, such as interrupt handling and system protection features.

When it is in slave mode, the QUICC can also be interfaced to any MC68030-type bus master instead of the

MC68EC040.

Freescale Semiconductor, Inc.

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