AD977 datasheet(23/24 Pages) AD

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AD977/AD977A

–23–

REV. D

The ADSP-2181 SPORT0 will now remain synchronized to the

external discontinuous clock for all subsequent conversions.

DR0

SCLK0

PF1

ADSP-2181

DATACLK

DATA

TAG

AD977/

AD977A

OSCILLATOR

RFS0

PF0

SPORT0 CNTRL REG = 0x300F

EXT/INT

R/C

Figure 30. AD977/AD977A to ADSP-2181 Interface

POWER SUPPLIES AND DECOUPLING

The AD977/AD977A has two power supply input pins. VANA

and VDIG provide the supply voltages to the analog and digital

portions, respectively. VANA is the 5 V supply for the on-chip

analog circuitry, and VDIG is the 5 V supply for the on-chip

digital circuitry. The AD977/AD977A is designed to be inde-

pendent of power supply sequencing and thus free from supply

voltage induced latchup.

With high performance linear circuits, changes in the power

supplies can result in undesired circuit performance. Optimally,

well regulated power supplies should be chosen with less than

1% ripple. The ac output impedance of a power supply is a

complex function of frequency and will generally increase with

frequency. Thus, high frequency switching, such as that encoun-

tered with digital circuitry, requires the fast transient currents

that most power supplies cannot adequately provide. Such a

situation results in large voltage spikes on the supplies. To com-

pensate for the finite ac output impedance of most supplies,

charge “reserves” should be stored in bypass capacitors. This

will effectively lower the supplies impedance presented to the

AD977/AD977A VANA and VDIG pins and reduce the magnitude

of these spikes. Decoupling capacitors, typically 0.1

µF, should

be placed close to the power supply pins of the AD977/AD977A

to minimize any inductance between the capacitors and the

VANA and VDIG pins.

The AD977/AD977A may be operated from a single 5 V

supply. When separate supplies are used, however, it is benefi-

cial to have larger capacitors, 10

µF, placed between the logic

supply (V

DIG) and digital common (DGND) and between the

analog supply (V

ANA) and the analog common (AGND2).

Additionally, 10

µF capacitors should be located in the vicinity

of the ADC to further reduce low frequency ripple. In systems

where the device will be subjected to harsh environmental noise,

additional decoupling may be required.

GROUNDING

The AD977/AD977A has three ground pins; AGND1, AGND2

and DGND. The analog ground pins are the “high quality”

ground reference points and should be connected to the system

analog common. AGND2 is the ground to which most internal

ADC analog signals are referenced. This ground is most sus-

ceptible to current induced voltage drops and thus must be

connected with the least resistance back to the power supply.

AGND1 is the low current analog supply ground and should be

the analog common for the external reference, input op amp

drive circuitry and the input resistor divider circuit. By applying

the inputs referenced to this ground, any ground variations will

be offset and have a minimal effect on the resulting analog input

to the ADC. The digital ground pin, DGND, is the reference

point for all of the digital signals that control the AD977/AD977A.

The AD977/AD977A can be powered with two separate power

supplies or with a single analog supply. When the system digital

supply is noisy, or fast switching digital signals are present, it is

recommended to connect the analog supply to both the V

ANA

and V

DIG pins of the AD977/AD977A and the system supply to

the remaining digital circuitry. With this configuration, AGND1,

AGND2 and DGND should be connected back at the ADC.

When there is significant bus activity on the digital output pins,

the digital and analog supply pins on the ADC should be

separated. This would eliminate any high speed digital noise

from coupling back to the analog portion of the AD977/

AD977A. In this configuration, the digital ground pin DGND

should be connected to the system digital ground and be

separate from the AGND pins.

BOARD LAYOUT

Designing with high resolution data converters requires careful

attention to board layout. Trace impedance is a significant issue.

A 1.22 mA current through a 0.5

Ω trace will develop a voltage

drop of 0.6 mV, which is 2 LSBs at the 16-bit level over the

20 volt full-scale range. Ground circuit impedances should be

reduced as much as possible since any ground potential differ-

ences between the signal source and the ADC appear as an error

voltage in series with the input signal. In addition to ground

drops, inductive and capacitive coupling needs to be considered.

This is especially true when high accuracy analog input signals

share the same board with digital signals. Thus, to minimize input

noise coupling, the input signal leads to VIN and the signal

return leads from AGND should be kept as short as possible.

In addition, power supplies should also be decoupled to filter

out ac noise.

Analog and digital signals should not share a common path.

Each signal should have an appropriate analog or digital return

routed close to it. Using this approach, signal loops enclose a

small area, minimizing the inductive coupling of noise. Wide PC

tracks, large gauge wire and ground planes are highly recom-

mended to provide low impedance signal paths. Separate analog

and digital ground planes are also recommended with a single

interconnection point to minimize ground loops. Analog signals

should be routed as far as possible from high speed digital sig-

nals and should only cross them, if absolutely necessary, at right

angles.

In addition, it is recommended that multilayer PC boards be used

with separate power and ground planes. When designing the

separate sections, careful attention should be paid to the layout.

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