AD5066

Rev. A | Page 17 of 24

POWER-ON RESET

The AD5066 contains a power-on reset circuit that controls

the output voltage during power-up. By connecting the POR

pin low, the AD5066 output powers up to 0 V; by connecting

the POR pin high, the AD5066 output powers up to midscale.

The output remains powered up at this level until a valid write

sequence is made to the DAC. This is useful in applications

where it is important to know the state of the output of the DAC

while it is in the process of powering up. There is also a software

executable reset function that resets the DAC to the power-on

reset code. Command 0111 is reserved for this reset function

(see Table 7). Any events on LDAC or CLR during power-on

reset are ignored.

Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function

MSB

LSB

DB31 to

DB28

DB27

DB26

DB25

DB24

DB23 to

DB20

DB10 to

DB19

DB9

DB8

DB4 to

DB7

DB3

DB2

DB1

DB0

X

0

1

0

0

X

X

PD1

PD0

X

DAC D

DAC C

DAC B

DAC A

Don’t

cares

Command bits (C2 to C0)

Address bits

(A3 to A0)—

don’t cares

Don’t

cares

Power-down

mode

Don’t

cares

Power-down/power-up channel

selection—set bit to 1 to select