AD5232

Data Sheet

Rev. C | Page 8 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

SDI

SDO

GND

W1

A1

CLK

B1

16

15

14

13

12

11

10

9

CS

PR

WP

W2

B2

A2

RDY

AD5232

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin

No.

Mnemonic

Description

1

CLK

Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.

2

SDI

Serial Data Input. The MSB is loaded first.

3

SDO

Serial Data Output. This open-drain output requires an external pull-up resistor. Command Instruction 9 and Command

Instruction 10 activate the SDO output (see Table 8). Other commands shift out the previously loaded SDI bit pattern

delayed by 16 clock pulses, allowing daisy-chain operation of multiple packages.

4

GND

Ground, Logic Ground Reference.

5

Negative Power Supply. Connect to 0 V for single-supply applications.

6

A1

Terminal A of RDAC1.

7

W1

Wiper Terminal W of RDAC1, ADDR (RDAC1) = 0x0.

8

B1

Terminal B of RDAC1.

9

B2

Terminal B of RDAC2.

10

W2

Wiper Terminal W of RDAC2, ADDR (RDAC2) = 0x1.

11

A2

Terminal A of RDAC2.

12

Positive Power Supply.

13

WP

Write Protect. When active low, WP prevents any changes to the present register contents, except PR, Command

Instruction 1, and Command Instruction 8, which refresh the RDACx register from EEMEM. Execute an NOP instruction

(Command Instruction 0) before returning WP to logic high.

14

PR

Hardware Override Preset. Refreshes the scratch pad register with current contents of the EEMEMx register. Factory

default loads Midscale 0x80 until EEMEMx is loaded with a new value by the user (PR is activated at the logic high

transition).

15

CS

Serial Register Chip Select, Active Low. Serial register operation takes place when CS returns to logic high.

16

RDY

Ready. This active-high, open-drain output requires a pull-up resistor. Identifies completion of Command Instruction 2,

Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and PR.