AD5663R datasheet(22/32 Pages) AD

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AD5623R/AD5643R/AD5663R

Data Sheet

Rev. F | Page 22 of 32

POWER-ON RESET

The AD5623R/AD5643R/AD5663R contain a power-on reset

circuit that controls the output voltage during power-up. The

AD5623R/AD5643R/AD5663R DACs output power up to 0 V,

and the output remains there until a valid write sequence is

made to the DACs. This is useful in applications where it is

important to know the state of the output of the DACs while

they are in the process of powering up. Any events on LDAC or

CLR during power-on reset are ignored.

SOFTWARE RESET

The AD5623R/AD5643R/AD5663R contain a software reset

function. Command 101 is reserved for the software reset

function (see Table 8). The software reset command contains

two reset modes that are software-programmable by setting bit

DB0 in the control register. Table 10 shows how the state of the

bit corresponds to the mode of operation of the device. Table 12

shows the contents of the input shift register during the

software reset mode of operation.

Table 10. Software Reset Modes

DB0

Registers Reset to Zero

DAC register

Input register

1 (Power-on Reset)

DAC register

Input register

LDAC register

Power-down register

Internal reference setup register

POWER-DOWN MODES

The AD5623R/AD5643R/AD5663R contain four separate

modes of operation. Command 100 is reserved for the power-

down function (see Table 8). These modes are software-

programmable by setting Bit DB5 and Bit DB4 in the control

the mode of operation of the device. Any or all DACs (DAC B

and DAC A) can be powered down to the selected mode by

setting the corresponding two bits (Bit DB1 and Bit DB0) to 1.

By executing the same Command 100, any combination of DACs

can be powered up by setting Bit DB5 and Bit DB4 to normal

operation mode.

Again, to select which combination of DAC channels to power

up, set the corresponding bits (Bit DB1 and Bit DB0) to 1. See

Table 13 for contents of the input shift register during power-

down/power-up operation.

The DAC output powers up to the value in the input register

while LDAC is low. If LDAC is high, the DAC ouput powers up

to the value held in the DAC register before power-down.

Table 11. Modes of Operation

DB5

DB4

Operating Mode

Normal operation

Power-down modes

1 kΩ to GND

100 kΩ to GND

Three-state

When both Bit DB1 and Bit DB2 are set to 0, the part works

normally, with its normal power consumption of 250 µA at 5 V.

However, for the three power-down modes, the supply current

falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply

current fall, but the output stage is also internally switched from

the output of the amplifier to a resistor network of known values.

This has the advantage that the output impedance of the part is

known while the part is in power-down mode. The outputs can

either be connected internally to GND through a 1 kΩ or 100 kΩ

resistor or left open-circuited (three-state) (see Figure 55).

RESISTOR

NETWORK

VOUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 55. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string,

and other associated linear circuitry are shut down when

power-down mode is activated. However, the contents of the

DAC register are unaffected when in power-down. The time

to exit power-down is typically 4 µs for both VDD = 5 V and

VDD = 3 V (see Figure 37).

Table 12. 24-Bit Input Shift Register Contents for Software Reset Command

MSB

LSB

DB23 to DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB1

DB0

1/0

Don’t care

Command bits (C2 to C0)

Address bits (A2 to A0)

Don’t care

Determines software reset mode

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