AD7851ARZ datasheet(6/36 Pages) AD

6 / 36 page

AD7851

–6–

REV. B

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams.

Figure 2 shows the reading and writing after conversion in

Interface Modes 2 and 3. To attain the maximum sample rate of

285 kHz in Interface Modes 2 and 3, reading and writing must

be performed during conversion. Figure 3 shows the timing dia-

gram for Interface Modes 4 and 5 with sample rate of 285 kHz.

At least a 330 ns acquisition time must be allowed (the time

from the falling edge of BUSY to the next rising edge of

CONVST) before the next conversion begins to ensure that the

part is settled to the 14-bit level. If the user does not want to

provide the

CONVST signal, the conversion can be initiated in

software by writing to the control register.

1.6mA

2.1V

200µA

50pF

OUTPUT

IOL

IOH

Figure 1. Load Circuit for Digital Output Timing

Specifications

DB15

DB0

DB11

POLARITY PIN LOGIC HIGH

SYNC (I/P)

SCLK (I/P)

BUSY (O/P)

CONVST (I/P)

DOUT (O/P)

DB0

DB11

DIN (I/P)

THREE-STATE

DB15

CONVERT

CONVERT = 3.25µs MAX, t1 = 100ns MIN,

5 = 30ns MAX, t7 = 30ns MIN

Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

POLARITY PIN LOGIC HIGH

SYNC ( O/P)

SCLK (O/P)

BUSY (O/P)

CONVST (I/P)

DOUT (O/P)

DB0

DB11

DIN (I/P)

DB15

DB0

THREE-STATE

DB11

THREE-STATE

DB15

CONVERT

CONVERT = 3.25µs MAX, t1 = 100ns MIN,

5 = 30ns MAX, t7 = 30ns MIN

Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

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