ADV7173KST datasheet(35/60 Pages) AD

35 / 60 page

REV. B

ADV7172/ADV7173

–35–

TIMING REGISTER 1 (TR17–TR10)

(Address (SR4–SR0) = 0BH)

Timing Register 1 is an 8-bit-wide register.

Figure 53 shows the various operations under the control of

Timing Register 1. This register can be read from as well writ-

ten to. This register can be used to adjust the width and position

of the master mode timing signals.

TR1 BIT DESCRIPTION

HSYNC Width (TR11–TR10)

These bits adjust the

HSYNC pulsewidth.

HSYNC to FIELD/VSYNC Delay (TR13–TR12)

These bits adjust the position of the

HSYNC output relative to

the FIELD/

VSYNC output.

HSYNC to FIELD Rising Edge Delay (TR15–TR14)

When the ADV7172/ADV7173 is in Timing Mode 1, these bits

adjust the position of the

HSYNC output relative to the FIELD

output rising edge.

VSYNC Width (TR15–TR14)

When the ADV7172/ADV7173 is configured in Timing Mode

2, these bits adjust the

VSYNC pulsewidth.

HSYNC to Pixel Data Adjust (TR17–TR16)

This enables the

HSYNC to be adjusted with respect to the pixel

data. This allows the Cr and Cb components to be swapped. This

adjustment is available in both master and slave timing modes.

TR11

TR10

TR17

TR12

TR13

TR15

TR16

TR14

HSYNC TO PIXEL

DATA ADJUST

TR17 TR16

TPCLK

HSYNC TO

FIELD/

VSYNC DELAY

TR13 TR12

TPCLK

HSYNC WIDTH

TPCLK

128

TPCLK

TR11 TR10

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

TB + 32 s

TR15 TR14

VSYNC WIDTH

(MODE 2 ONLY)

TPCLK

128

TPCLK

LINE 313

LINE 314

LINE 1

TIMING MODE 1 (MASTER/PAL)

HSYNC

FIELD/

VSYNC

TR15 TR14

Figure 53. Timing Register 1

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