AD7538

Rev. B | Page 13 of 16

APPLICATION HINTS

OUTPUT OFFSET

CMOS DACs in circuits such as Figure 6 and Figure 8 exhibit

a code dependent output resistance, which in turn can cause a

code dependent error voltage at the output of the amplifier.

The maximum amplitude of this error, which adds to the DAC

a suitable op amp. The op amp has a wide bandwidth and high

slew rate and is recommended for ac and other applications

requiring fast settling.

GENERAL GROUND MANAGEMENT

Because the AD7538 is specified for high accuracy, it is impor-

tant to use a proper grounding technique. AC or transient

voltages between AGND and DGND can cause noise injection

into the analog output. The simplest method of ensuring that

voltages at AGND and DGND are equal is to tie AGND and

DGND together at the AD7538. In more complex systems

where the AGND and DGND intertie on the backplane, it is

recommended that two diodes be connected in inverse

parallel between the AD7538 AGND and DGND pins

(1N914 or equivalent).

MICROPROCESSOR INTERFACING

The AD7538 is designed for easy interfacing to 16-bit micro-

processors and can be treated as a memory mapped peripheral.

This reduces the amount of external logic needed for interfacing

to a minimal.

AD7538-TO-8086 INTERFACE

Figure 10 shows the 8086 processor interface to a single device.

In this setup, the double buffering feature (using LDAC) of the

DAC is not used. The 14-bit word is written to the DAC in one

MOVE instruction and the analog output responds

immediately.

ADDRESS BUS

DATA BUS

AD0 TO AD15

WR

ALE

AD13

AD0

CS

LDAC

WR

DB0 TO DB13

8096

16-BIT

LATCH

ADDRESS

DECODE

Figure 10. AD7538-to-8086 Interface Circuit

In a multiple DAC system, the double buffering of the AD7538

allows the user to simultaneously update all DACs. In Figure 11,

a 14-bit word is loaded to the input registers of each of the DACs

in sequence. Then, with one instruction to the appropriate

address, CS4 (that is, LDAC) is brought low, updating all the

DACs simultaneously.

ADDRESS BUS

DATA BUS

AD0 TO AD15

WR

ALE

CS

LDAC

WR

DB0 TO DB13

8096

16-BIT

LATCH

ADDRESS

DECODE

CS4 CS3 CS2

CS1

CS

LDAC

WR

DB0 TO DB13

CS

LDAC

WR

DB0 TO DB13

Figure 11. AD7538-to-8086 Interface: Multiple DAC System

AD7538-TO-MC68000 INTERFACE

Figure 12 shows the MC68000 processor interface to a single

device. In this setup, the double buffering feature of the DAC

is not used and the appropriate data is written into the DAC in

one MOVE instruction.

ADDRESS BUS

DATA BUS

ADDRESS

DECODE

D0 TO D15

A1 TO A23

R/W

DTACK

AS

CS

LDAC

WR

DB0 TO DB13

MC68000

Figure 12. AD7538-to-MC68000 Interface