REV. A

AD7716

–12–

Control register bit, DB15 (A3), acts as an extra address bit

which must always be set to 1 to enable programming of the

AD7716. If it is set to 0, then the programmed word is ignored.

This allows the user to bypass the AD7716 control register and

use the serial stream from the DSP or microcomputer to pro-

gram other serial peripheral devices.

When a valid word has been received, the device interrogates

the M0 bit. If this is 0, then the digital filter cutoff frequencies

are programmed to the appropriate value if the device address

pins correspond to the A2, A1, A0 bits in the control register. If

the device address pins do not correspond to the A2, A1, A0

bits then the FC2, FC1, FC0 bits are ignored. If M0 is 1, then

the digital filter cutoff frequencies are programmed to the FC2,

FC1, FC0 value irrespective of the address bits. In a multi-

channel system this allows the user to either program all

AD7716s to have the same cutoff frequency or else to give each

device a separate cutoff frequency.

Control register bits FC2, FC1, FC0 program the digital filter

cutoff frequency, see Table VI.

Control register bits D2, D1 control the digital output pins D2

and D1. These are programmed in the same way as FC2, FC1,

FC0.

CONTROL REGISTER DESCRIPTION

The 16-bit control register is programmed in two 8-bit bytes;

the low byte is programmed first and the high byte second. The

loading format is LSB first (DB0 for the Least Significant Byte;

DB8 for the Most Significant Byte). Three control lines are

used: TFS, SCLK and SDATA. On initial application of

power to the AD7716, the control register will come up in an

undetermined state. Programming the control register requires

an SCLK input, a TFS input and an SDATA input. The

MODE pin on the device determines whether it is in the master

interface mode or the slave interface mode. In either mode, a

falling edge on TFS causes the part to relinquish control of the

SDATA and SCLK lines. When TFS goes low, data on the

SDATA line is clocked into the control register on each suc-

ceeding falling edge of SCLK. When 8 bits have been clocked

in, the transfer automatically stops. Only when another negative

going edge is detected on TFS will new information be written

into the control register. The control register programming

model is shown in Table II. Bits DB8 and DB0 allow the con-

trol register to identify whether the MS Byte or the LS Byte has

been programmed. Only when DB8 is a 1 and DB0 is a 0 will

the register recognize that a complete valid word has been

programmed.

Table II. Control Register Programming Model

Most Significant Byte

Least Significant Byte

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

A3

A2

A1

A0

M0

FC2

FC1

1

FC0

DOUT2 DOUT1

X

X

X

X

0

Table III. M0 Truth Table

M0

Programming Mode

0

A2, A1, A0 determine which device is addressed and

programmed with cutoff frequency and digital output.

1

A2, A1, A0 ignored. All devices are addressed and

programmed with common cutoff frequency and digital

output.

Table IV. Cutoff Frequency Truth Table

FC2

FC1

FC0

Cutoff Frequency (Hz)

000

584

001

292

010

146

011

73

1

0

0

36.6