DAC5675

SLAS352C − DECEMBER 2001 − REVISED AUGUST 2004

9

www.ti.com

clock input and timing (continued)

Figure 7 shows the equivalent schematic of the differential clock input buffer. The input nodes are internally

self-biased enabling ac coupling of the clock inputs. Figure 8 shows the preferred configuration for driving the

DAC5675.

Ropt

22

Ω

Node CLKC

Internally Biased

DAC5675

TTL/CMOS Source

0.01

µF

CLK

CLKC

Figure 7. Driving the DAC5675 With a Single-Ended TTL/CMOS Clock Source

RT

50

Ω

DAC5675

CAC

0.01

µF

CAC

0.01

µF

RT

50

Ω

VTT

Differential

ECL

or

(LV)PECL

Source

+

−

CLK

CLKC

Figure 8. Driving the DAC5675 With a Differential ECL/PECL Clock Source

RT

50

Ω

DAC5675

CAC

0.01

µF

CAC

0.01

µF

RT

50

Ω

VTT

Single-Ended

ECL

or

(LV)PECL

Source

ECL/PECL

Gate

CLK

CLKC

Figure 9. Driving the DAC5675 With a Single-Ended ECL/PECL Clock Source