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ALD521DPD Datasheet(PDF) 3 Page - Advanced Linear Devices

Part # ALD521DPD
Description  24 BIT SERIAL INTERFACE DIGITAL CONTROLLER
PDF  6 Pages
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Manufacturer  ALD [Advanced Linear Devices]
Direct Link  http://www.aldinc.com
Logo ALD - Advanced Linear Devices

ALD521DPD Datasheet(HTML) 3 Page - Advanced Linear Devices

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ALD512D
Advanced Linear Devices
3
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+
+7.0V
Differential input voltage range
-0.3V to V+ +0.3V
Power dissipation
600 mW
Operating temperature range
PD, SD package
0
°C to +70°C
Storage temperature range
-65
°C to +150°C
Lead temperature, 10 seconds
+260
°C
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25
oC V+ = +5V unless otherwise specified
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Supply
Operating Voltage Range
V+
3
5
5.5
V
Supply Current
IDD
4.0
6.8
mA
Input Characteristics
Low Input Voltage
VIL
-0.3
1.0
V
High Input Voltage
VIH
3.5
5.3
V
Input Leakage Current
IIL
-10
10
µA
Output Characteristics
Low Output Voltage
VOL
0.2
0.8
V
High Output Voltage
VOH
3.6
4.8
V
CL = 10pF. Rise/Fall Times
tR , tF
25
125
nsec
Oscillator (OSCIN, OSCOUT)
Crystal Frequency
fXTL
3.6864
4.0
MHz
External Frequency (OSCIN)
fOSC
4.0
MHz
Timing Characteristics
Power Up Delay Time
tPU
36
msec
Chip Select Setup Time1
tCS
1.1
µsec
Chip Select Delay Time1
tCD
1
Conv. Cycle
Data Valid Setup Time
tDV
18
µsec
Data Valid Time Out Time
tTO
5.5
msec
Data Out Time
tDOUT
500
nsec
Serial Clock Low Time
tSC
11
25
µsec
Data Not Valid Time
tDNV
15
µsec
Integration Time 2
tINT
16.666
300
msec
Integrator ZERO Time
tINTZ
2
msec
Autozero Time
tAZ
tINT
msec
1 Chip Select Delay time (tCD) may be as short as 7 µsec, if start of auto zero phase cycle time could be
determined. For asynchoronous operation, tCD must be for a minimum of one complete conversion cycle to
assure synchronization to start of auto zero phase cycle time.
2 These are typical practical limits for Integration time. Lower Integration time than the minimum allows more
conversion cycles per second at reduced count resolution.
Higher Integration time increases count
resolution, but requires increased capacitor value and lowered number of conversion cycles per second.
Deintegration time depends on selection of full scale input range, integration capacitor value and voltage
reference.
3 ESD Sensitive Device. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to device and may affect device reliability.



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