CAB4A datasheet(2/10 Pages) TI1

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DA[13:0], DBA[1:0],

Control Word

State Machine and

Control Logic

DCS[1:0]_n,

DCKE0,

DODT0,

DCKE1

DODT1

PLL

Output-Enable

Y0..Y3, BCK-

Enable

VrefCA

QAA[13:0], QABA[1:0]

QACS[1:0]_n,

Y1_t

Y1_c

Y0_t

Y0_c

Y2_t

Y2_c

Y3_t

Y3_c

CK_t

CK_c

DRST_n

10k

100k

CS Logic

DA[13:0],

DBA[1:0],

DBG[1:0],

QABG[1:0], QxACT_n

QBA13, QBA11,

QBBA[1;0]

QBBG[1:0],

QBCS[1:0]_n,

QACKE[1:0]

QBCKE[1:0]

QAODT[1:0]

QBODT[1:0]

DACT_n

DBG[1:0], DACT_n,DPAR

Feedback

QAC2

QBC2

QRST_n

DCS2_n/DC0,

DC2

DCS3_n/DC1,

QACS2_n/C0,

QACS3_n/C1,

QBCS2_n/C0,

QBCS3_n/C1,

DA17,

DRAS_n/A16,

DCAS_n/A15,

DWE_n/A14,

DA17,DRAS_n/A16,

DCAS_n/A15, DWE_n/A14

QxRAS_n/QxA16,

QxCAS_n/QxA15,

QxWE_n/QxA14,

QBA17,

QBA[9,3],

QBA12, QBA10,QAA17

QBA[2:0], QAPAR

I2C

VDDSPD

SCL

SDA

SA[2:0]

BFUNC

ZQCal

BCK_t

BCK_c

DQB Interface

Command Decoder

BCOM[3:0]

BCKE

BODT

DPAR

QBPAR (cond.)

ERROR_IN_n

Parity Logic

ALERT_n

Vref Generation

and Control

and Decoder

QVREFCA

BVREFCA

Vref for Input Receivers

CW Table

120k

CAB4A

SNAS630B – JULY 2013 – REVISED OCTOBER 2013

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

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