TDA2

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SPRT680 – OCTOBER 2013

ADAS Applications Processor

TDA2x System-on-Chip Technical Brief

1

Advanced Driver Assistance System (ADAS) TDA2x System-on-Chip

1.1

Features

1

– Interrupt Controller Supporting 64 Input

• Architecture Designed for ADAS Applications

Events

– Best-in-Class CPU Performance

• General-Purpose Memory Controller (GPMC)

– State-of-the-Art Integrated Power

• Enhanced Direct Memory Access (EDMA)

Management

Controller

– Video, Image, and Graphics Processing

• 3-Port Gigabit Ethernet (GMAC)

Support

– Up to Two External Ports, One Internal

•

Streaming Full-HD Video (1920x1080p, 60

fps)

• Dual Controller Area Network (DCAN) Modules

•

Multiple Video Input and Video Output

– CAN 2.0B Protocol

•

2D and 3D Graphics

• PCI Express 2.0 Port with Integrated PHY

• ARM® Dual Cortex™-A15 Microprocessor

– Single Port With 1 Lane at 5.0 Gbps

Subsystem

• Sixteen 32-Bit General-Purpose Timers

• C66x™ Floating-Point VLIW DSP

• 32-Bit MPU Watchdog Timer

– Fully Object-Code Compatible with C67x™

• Ten Configurable UART/IrDA/CIR Modules

and C64x+™

• Four Multichannel Serial Peripheral Interfaces

– Up to Thirty-two 16 x 16-bit Fixed-point

(MCSPIs)

Multiplies per Cycle

• Up to 2.5 MiB of On-Chip L3 RAM

• Multichannel Audio Serial Port (MCASP)

• 768-Bit Interface to Internal RAM

• Up to 256 General-Purpose I/O (GPIO) Pins

• Level 3 (L3) and Level 4 (L4) Interconnects

• Power, Reset, and Clock Management

• Two DDR2/DDR3 Memory Interface (EMIF)

– SmartReflex™ Class-1 Technology

Modules

– Multiple Independent Core Power Domains

– Supports up to DDR2-667 and DDR3-667

– Multiple Independent Core Voltage Domains

– Up to 2-GiB Supported per EMIF

– Clock Management (CM) Allows Reduction

• ARM Cortex™-M4 Image Processor (IPU)

of Dynamic Consumption

– Two Dual-core, 200 MHz per Core

• On-Chip Debug with CTools Technology

• Vision AccelerationPac

• Automotive AEC-Q100 Qualified

– Up to Four Embedded Vision Engines (EVEs)

• 28-nm CMOS Technology

• IVA-HD Subsystem

• The ADAS Vision28 Will Be Offered with Two

• Display Subsystem

Package Options:

– Display Controller with DMA Engine and Up

– 23-mm Package (ABC Suffix)

to Three Pipelines

•

Ball Grid Array (BGA)

– HDMI Encoder: HDMI 1.4a, HDCP 1.4, and

•

0.8-mm Ball Pitch with Via Channel Array

DVI 1.0 Compliant

(VCA)

• 2D-Graphics Accelerator (BB2D) Subsystem

•

Partial Grid

– Vivante™ GC320 Core

•

760 Device Pins

• Video Processing Engine (VPE)

– 17-mm Package (AAS Suffix)

• Available Dual-Core PowerVR® SGX544™ 3D

•

BGA

GPU

•

0.65-mm Ball Pitch with Microvia

• Up to 3 Video Input Port (VIP) Module Instances

•

Full Grid

– Support for Up to 10 Multiplexed Input Ports

•

625 Device Pins

• Available Programmable Real-time Unit (PRU)

Subsystem

1

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PRODUCT PREVIEW information concerns products in the formative or design phase of

Copyright © 2013, Texas Instruments Incorporated

development. Characteristic data and other specifications are design goals. Texas

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