TAS5731MPHPR datasheet(25/68 Pages) TI1

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TAS5731M

www.ti.com

SLOS838B – JULY 2013 – REVISED NOVEMBER 2013

DETAILED DESCRIPTION

POWER SUPPLY

To facilitate system design, the TAS5731M needs only a 3.3-V supply in addition to the PVDD power-stage

supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all

circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap

circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is

designed as identical half-bridges with separate bootstrap pins (BST_x). The gate-drive voltage (GVDD_OUT) is

derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to

their associated pins as possible. Inductance between the power-supply pins and decoupling capacitors must be

avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the

bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output

potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM

switching frequencies in the range from 288 kHz to 384 kHz, it is recommended to use 10-nF, X7R ceramic

capacitors, size 0603 or 0805, for the bootstrap supply. These 10-nF capacitors ensure sufficient energy storage,

even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during

the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is

decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5731M is fully protected against erroneous power-stage turnon due to parasitic gate charging.

2C Address Selection and Fault Output

ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the

Typical Application Circuit section in order to set the I2C address. Pulling this pin HIGH through the resistor

results in setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in

setting the address to 0011010 (0x34).

During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault

notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to its

default state when register 0x02 is cleared. The behavior of the pin in response to a fault condition is to be pulled

low immediately upon an error. The device then waits for a period of time determined by BKND_ERR Register

(0x1C) before attempting to resume playback. If the error has been cleared when the device attempts to resume

playback, playback will resume, the ADR/FAULT pin will remain high, and normal operation will resume. If the

error has not been removed, then the device will immediately re-enter the protected state and wait again for the

predetermined period of time to pass. The device will pull the fault pin low for over-current, over-temperature, and

under-voltage lock-out.

SINGLE-FILTER PBTL MODE

The TAS5731M supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected

before the LC filter. In addition to connecting OUT_A/OUT_B and OUT_C/OUT_D, BST_A/BST_B and

BST_C/BST_D must also be connected before the LC filter, as shown in the SIMPLIFIED PBTL APPLICATION

DIAGRAM. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff

of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge. There is a

pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.

PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should

be written with a value of 0x0110 3245.

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