3952

FULL-BRIDGE

PWM MOTOR DRIVER

The following procedure can be used to evaluate the

worst-case slow-decay internal PWM load current regula-

tion in the system:

Set V

current control operating in slow-decay mode, use an

oscilloscope to measure the time the output is low (sink

ON) for the output that is chopping. This is the typical

minimum ON time (t

should be increased until the measured value of t

equal to t

characteristics table. When the new value of C

set, the value of R

t

equal to 105% of the nominal design value. The worst-

case load current regulation then can be measured in the

system under operating conditions.

In applications utilizing both fast- and slow-decay

internal PWM modes, the performance of the slow-decay

current regulation should be evaluated per the above

procedure and a t

a C

cient blanking during fast-decay internal PWM.

LOAD CURRENT REGULATION WITH EXTERNAL

PWM OF THE PHASE AND ENABLE INPUTS

The PHASE and ENABLE inputs can be pulse-width

modulated to regulate load current. Typical propagation

delays from the PHASE and ENABLE inputs to transitions

of the power outputs are specified in the electrical charac-

teristics table. If the internal PWM current control is used,

then the comparator blanking function is active during

phase and enable transitions. This eliminates false

tripping of the over-current comparator caused by switch-

ing transients (see “RC Blanking” above).

With the MODE input low, toggling the ENABLE input

turns ON and OFF the selected source and sink drivers.

The corresponding pair of flyback and ground clamp

diodes conduct after the drivers are disabled, resulting in

fast current decay. When the device is enabled, the

internal current control circuitry will be active and can be

used to limit the load current in a slow-decay mode.

For applications that PWM the ENABLE input, and

desire that the internal current limiting circuit function in the

fast-decay mode, the ENABLE input signal should be

inverted and connected to the MODE input. This prevents

the device from being switched into sleep mode when the

ENABLE input is low.

Toggling the PHASE terminal determines/controls

which sink/source pair is enabled, producing a load current

that varies with the duty cycle and remains continuous at

all times. This can have added benefits in bidirectional

brush dc servo motor applications as the transfer function

between the duty cycle on the phase input and the aver-

age voltage applied to the motor is more linear than in the

case of ENABLE PWM control (which produces a discon-

tinuous current at low current levels). See also, “DC Motor

Applications” below.

SYNCHRONOUS FIXED-FREQUENCY PWM

The internal PWM current-control circuitry of multiple

A3952S– devices can be synchronized by using the simple

circuit shown in figure 3. A 555 IC can be used to gener-

ate the reset pulse/blanking signal (t

the PWM cycle (t

of 1.5

µs in slow-decay mode and 2 µs in fast-decay

mode. When used in this configuration, the R

components should be omitted. The PHASE and ENABLE

inputs should not be PWMed with this circuit configuration

due to the absence of a blanking function synchronous

with their transitions.

Figure 3 — Synchronous Fixed-Frequency Control Circuit

MISCELLANEOUS INFORMATION

A logic high applied to both the ENABLE and MODE

terminals puts the device into a sleep mode to minimize

current consumption when not in use.

An internally generated dead time prevents crossover

currents that can occur when switching phase or braking.

Thermal protection circuitry turns OFF all drivers

should the junction temperature reach 165

°C (typical).

This is intended only to protect the device from failures

due to excessive junction temperatures and should not

Dwg. EP-060

1N4001

2N2222

V

CC

t

1

2

t