A3957SLB datasheet(8/16 Pages) ALLEGRO

8 / 16 page

3957

FULL-BRIDGE PWM

MICROSTEPPING

MOTOR DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

Terminal Functions

A3957SA

A3957SLB

Terminal

Lead

Name

Description

–

No internal connection.

PFD

(Percent Fast Decay) The analog input used to set the current-decay mode.

REF

(VREF) The voltage at this input (along with the value of RS and the states of DAC

inputs D0, D1, and D2) set the peak output current.

–

No internal connection.

The parallel combination of external resistor RT and capacitor CT set the off time

for the PWM current regulator. CT also sets the blanking time.

6-7

GROUND

Return for the logic supply (VCC) and load supply (VBB); the reference for all

voltage measurements.

(DATA3) One of four (MSB) control bits for the internal digital-to-analog converter.

LOGIC SUPPLY

(VCC) Supply voltage for the logic circuitry. Typically = 5 V.

PHASE

The PHASE input determines the direction of current in the load.

(DATA2) One of four control bits for the internal digital-to-analog converter.

–

No internal connection.

(DATA1) One of four control bits for the internal digital-to-analog converter.

–

No internal connection.

OUTA

One of two output load connections.

–

No internal connection.

SENSE

Connection to the sink-transistor emitters. Sense resistor RS is connected

between this point and ground.

–

No internal connection.

18-19

GROUND

Return for the logic supply (VCC) and load supply (VBB); the reference for all

voltage measurements.

220

(DATA0) One of four (LSB) control bits for the internal digital-to-analog converter.

–

No internal connection.

OUTB

One of two output load connections.

LOAD SUPPLY

(VBB) Supply voltage for the load.

–

No internal connection.

* For the ‘A’ package, pins 1 and 8 must be externally connected together.

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