ADS7841EB datasheet(13/19 Pages) TI

13 / 19 page

ADS7841

SBAS084B

Data Format

The ADS7841 output data is in straight binary format, as

shown in Figure 7. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

FS = Full-Scale Voltage = V

REF

1LSB = V

REF/4096

FS – 1LSB

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

Note 1: Voltage at converter input, after

multiplexer: +IN – (–IN). See Figure 2.

Input Voltage(1) (V)

FIGURE 7. Ideal Input Voltages and Output Codes.

8-Bit Conversion

The ADS7841 provides an 8-bit conversion mode that can

be used when faster throughput is needed and the digital

result is not as critical. By switching to the 8-bit mode, a

conversion is complete four clock cycles earlier. This could

be used in conjunction with serial interfaces that provide a

12-bit transfer or two conversions could be accomplished

with three 8-bit transfers. Not only does this shorten each

conversion by four bits (25% faster throughput), but each

conversion can actually occur at a faster clock rate. This is

because the internal settling time of the ADS7841 is not as

critical, settling to better than 8 bits is all that is needed. The

clock rate can be as much as 50% faster. The faster clock

rate and fewer clock cycles combine to provide a 2x increase

in conversion rate.

POWER DISSIPATION

There are three power modes for the ADS7841: full power

(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),

and shutdown (SHDN LOW). The affects of these modes

varies depending on how the ADS7841 is being operated. For

example, at full conversion rate and 16 clocks per conver-

sion, there is very little difference between full power mode

and auto power-down. Likewise, if the device has entered

auto power-down, a shutdown (SHDN LOW) will not lower

power dissipation.

When operating at full-speed and 16-clocks per conversion

(see Figure 4), the ADS7841 spends most of its time acquir-

ing or converting. There is little time for auto power-down,

assuming that this mode is active. Thus, the difference

between full power mode and auto power-down is negli-

gible. If the conversion rate is decreased by simply slowing

the frequency of the DCLK input, the two modes remain

approximately equal. However, if the DCLK frequency is

kept at the maximum rate during a conversion, but conver-

sion are simply done less often, then the difference between

the two modes is dramatic. Figure 8 shows the difference

between reducing the DCLK frequency (“scaling” DCLK to

match the conversion rate) or maintaining DCLK at the

highest frequency and reducing the number of conversion

per second. In the later case, the converter spends an increas-

ing percentage of its time in power-down mode (assuming

the auto power-down mode is active).

If DCLK is active and CS is LOW while the ADS7841 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH. The differences in

supply current for these two cases are shown in Figure 9.

Operating the ADS7841 in auto power-down mode will

result in the lowest power dissipation, and there is no

conversion time “penalty” on power-up. The very first

conversion will be valid. SHDN can be used to force an

immediate power-down.

FIGURE 8. Supply Current vs Directly Scaling the Fre-

quency of DCLK with Sample Rate or Keeping

DCLK at the Maximum Possible Frequency.

10k

100k

SAMPLE (Hz)

100

1000

CLK = 2MHz

CLK = 16 • fSAMPLE

A = 25°C

CC = +2.7V

REF = +2.5V

PD1 = PD0 = 0

FIGURE 9. Supply Current vs State of CS.

10k

100k

SAMPLE (Hz)

0.00

0.09

CS LOW

(GND)

CS HIGH (+V

CC)

A = 25°C

CC = +2.7V

REF = +2.5V

CLK = 16 • fSAMPLE

PD1 = PD0 = 0

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