LM555QML

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SNOSAP2C – AUGUST 2005 – REVISED APRIL 2013

Figure 26. 50% Duty Cycle Oscillator

ADDITIONAL INFORMATION

Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1

μF

in parallel with 1

μF electrolytic.

Lower comparator storage time can be as long as 10

μs when pin 2 is driven fully to ground for triggering. This

limits the monostable pulse width to 10

μs minimum.

Delay time reset to output is 0.47

μs typical. Minimum reset pulse width must be 0.3μs, typical.

Pin 7 current switches within 30ns of the output (pin 3) voltage.

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