PIC16 datasheet(205/418 Pages) MICROCHIP

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DS40001609C-page 205

PIC16(L)F1508/9

21.5.3.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPxCON3 register

enables additional clock stretching and interrupt gen-

eration after the eighth falling edge of a received

matching address. Once a matching address has

been clocked in, CKP is cleared and the SSPxIF inter-

rupt is set.

Figure 21-19 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

Bus starts idle.

Master sends Start condition; the S bit of

SSPxSTAT is set; SSPxIF is set if interrupt on

Start detect is enabled.

Master sends matching address with R/W bit

set. After the eighth falling edge of the SCLx line

the CKP bit is cleared and SSPxIF interrupt is

generated.

Slave software clears SSPxIF.

Slave software reads ACKTIM bit of SSPxCON3

Slave reads the address value from the

SSPxBUF register clearing the BF bit.

Slave software decides from this information if it

wishes to ACK or not ACK and sets the ACKDT

bit of the SSPxCON2 register accordingly.

Slave sets the CKP bit releasing SCLx.

Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSPxIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPxIF.

12. Slave loads value to transmit to the master into

SSPxBUF setting the BF bit.

13. Slave sets the CKP bit, releasing the clock.

14. Master clocks out the data from the slave and

sends an ACK value on the ninth SCLx pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPxCON2 register.

16. Steps 10-15 are repeated for each byte trans-

mitted to the master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: SSPxBUF cannot be loaded until after the

ACK.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCLx

line to receive a Stop.

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