PIC16 datasheet(167/418 Pages) MICROCHIP

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DS40001609C-page 167

PIC16(L)F1508/9

19.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

19.4

Timer1 (Secondary) Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins S1OSI (input) and S1OSO (ampli-

fier output). This internal circuit is to be used in con-

junction with an external 32.768 kHz crystal. The

oscillator circuit is enabled by setting the T1OSCEN bit

of the T1CON register. The oscillator will continue to

run during Sleep.

19.5

Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 19.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

19.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register

pair.

19.6

Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Enable.

Timer1 gate can also be driven by multiple selectable

sources.

19.6.1

TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 19-3 for timing details.

19.6.2

TIMER1 GATE SOURCE

SELECTION

Timer1 gate source selections are shown in Table 19-4.

Source selection is controlled by the T1GSS<1:0> bits

of the T1GCON register. The polarity for each available

source is also selectable. Polarity selection is controlled

by the T1GPOL bit of the T1GCON register.

TABLE 19-4:

TIMER1 GATE SOURCES

Note:

The oscillator requires some time to start-up

and stabilize before use. The SOSCR bit in

the OSCSTAT register monitors the

oscillator and indicates when the oscillator is

ready for use. When T1OSCEN is set, the

SOSCR bit is cleared. After 1024 cycles of

the oscillator are countered, the SOSCR bit

is set, indicating that the oscillator should be

stable and ready for use.

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

TABLE 19-3:

TIMER1 GATE ENABLE

SELECTIONS

T1CLK

T1GPOL

T1G

Timer1 Operation



Counts



Holds Count



Holds Count



Counts

T1GSS

Timer1 Gate Source

Timer1 Gate pin (T1G)

Overflow of Timer0 (T0_overflow)

(TMR0 increments from FFh to 00h)

Comparator 1 Output (C1OUT_sync)(1)

Comparator 2 Output (C2OUT_sync)(1)

Note 1:

Optionally synchronized comparator output.

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