MCP73853 datasheet(17/24 Pages) MICROCHIP

17 / 24 page

 2004 Microchip Technology Inc.

DS21915A-page 17

MCP73853/55

6.1

Application Circuit Design

Due to the low efficiency of linear charging, the most

important factors are thermal design and cost. These

are a direct function of the input voltage, output current

and thermal impedance between the battery charger

and the ambient cooling air. The worst-case situation

exists when the device has transitioned from the

Preconditioning mode to the Constant-current mode. In

this situation, the battery charger has to dissipate the

maximum power. A trade-off must be made between

the charge current, cost and thermal requirements of

the charger.

6.1.1

COMPONENT SELECTION

Selection of the external components in Figure 6-1 is

crucial to the integrity and reliability of the charging sys-

tem. The following discussion is intended to be a guide

for the component selection process.

6.1.1.1

CURRENT PROGRAMMING RESISTOR

(RPROG)

The preferred fast charge current for Lithium-Ion cells

is at the 1C rate, with an absolute maximum current at

the 2C rate. For example, a 500 mAH battery pack has

a preferred fast charge current of 500 mA. Charging at

this rate provides the shortest charge cycle times

without degradation to the battery pack performance or

life.

400 mA is the typical maximum charge current

obtainable from the MCP7385X devices. For this situa-

tion, the PROG input should be connected directly to

VSS.

6.1.1.2

THERMAL CONSIDERATIONS

The worst-case power dissipation in the battery

charger occurs when the input voltage is at the

maximum and the device has transitioned from the

Preconditioning mode to the Constant-current mode. In

this case, the power dissipation is:

Where

VDDMAX is the maximum input voltage

(IREGMAX) is the maximum fast charge current, and

VPTHMIN is the minimum transition threshold voltage.

Power dissipation with a 5V, +/-10% input voltage

source is:

With the battery charger mounted on a 1 in2 pad of

1 oz. copper, the junction temperature rise is approxi-

mately 50°C. This would allow for a maximum operat-

ing ambient temperature of 35°C before thermal

regulation is entered.

6.1.1.3

EXTERNAL CAPACITORS

The MCP7385X devices are stable with or without a

battery load. In order to maintain good AC stability in

the Constant-voltage mode, a minimum capacitance of

4.7 µF is recommended to bypass the VBAT pin to VSS.

This capacitance provides compensation when there is

no battery load. In addition, the battery and intercon-

nections appear inductive at high frequencies. These

elements are in the control feedback loop during

Constant-voltage

mode.

Therefore,

the

bypass

capacitance may be necessary to compensate for the

inductive nature of the battery pack.

Virtually any good quality output filter capacitor can be

used,

independent

the

capacitor’s

minimum

Effective Series Resistance (ESR) value. The actual

value of the capacitor (and its associated ESR)

depends on the output load current. A 4.7 µF ceramic,

tantalum or aluminum electrolytic capacitor at the

output is usually sufficient to ensure stability for up to

the maximum output current.

6.1.1.4

REVERSE BLOCKING PROTECTION

The MCP7385X devices provide protection from a

faulted or shorted input or from a reversed-polarity

input source. Without the protection, a faulted or

shorted input would discharge the battery pack through

the body diode of the internal pass transistor.

6.1.1.5

ENABLE INTERFACE

In the stand-alone configuration, the enable pin is gen-

erally tied to the input voltage. The MCP7385X devices

automatically enter a low power mode when voltage on

the VDD input falls below the UVLO voltage (VSTOP),

reducing the battery drain current to 0.28 µA, typically.

6.1.1.6

CHARGE STATUS INTERFACE

Two status outputs provide information on the state of

charge. The current-limited, open-drain outputs can be

used to illuminate external LEDs. Refer to Table 5-1

and Table 5-2 for a summary of the state of the status

output during a charge cycle.

6.2

PCB Layout Issues

For optimum voltage regulation, place the battery pack

as close as possible to the device’s VBAT and VSS pins.

It is recommended that the designer minimize voltage

drops along the high-current-carrying PCB traces.

If the PCB layout is used as a heatsink, adding many

vias in the heatsink pad can help conduct more heat to

the backplane of the PCB, thus reducing the maximum

junction temperature.

Pow erDiss ipation

DDMAX

PTHMIN

–

() I

REGMAX

PowerD issipation

5.5V

2.7V

–

() 475mA

1.33W

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