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Functional Timing Tests

AC timing for logic module internal delays is determined

after place and route. The DirectTime Analyzer utility

displays actual timing parameters for circuit delays. ACT 1

devices are AC tested to a “binning” circuit specification.

The circuit consists of one input buffer + n logic modules +

one output buffer (n = 16 for A1010B; n = 28 for A1020B). The

logic modules are distributed along two sides of the device, as

inverting or non-inverting buffers. The modules are

connected through programmed antifuses with typical

capacitive loading.

following AC test specifications.

Output Buffer Performance Derating (5V)

Note:

The above curves are based on characterizations of sample devices and are not completely tested on all devices.

Output Buffer Performance Derating (3.3V)

Note:

The above curves are based on characterizations of sample devices and are not completely tested on all devices.

Sink

12

10

8

6

4

0.2

0.3

0.4

0.5

0.6

Source

–4

–6

–8

–10

–12

4.0

3.6

3.2

2.8

2.4

2.0

Military, worst-case values at 125

°C, 4.5 V.

Commercial, worst-case values at 70

°C, 4.75 V.

Sink

12

10

8

6

4

0.0

0.1

0.2

0.3

0.4

Source

–4

–6

–8

–10

–12

0

0.5

1.0

1.5

2.0

2.5

Commercial, worst-case values at 70

°C, 4.75 V.